Semiconductor memory device operable to write data accurately at

Details Semiconductor memory device operable to write data accurately at Semiconductor memory device operable to write data accurately at

1995-09-11

1997-05-13

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36518901, 36518911, G11C 700

Patent

active

056299001

ABSTRACT:
A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

REFERENCES:
patent: 4337523 (1982-06-01), Hotta et al.
patent: 4982372 (1991-01-01), Matsuo
patent: 5262919 (1993-11-01), Kuriyama et al.
patent: 5355342 (1994-10-01), Ueoka
patent: 5392242 (1995-02-01), Koike
"A 12-NS ECL I/O 256KX1-Bit SRAM Using A 1.mu.MBicMOStechnology", Robert Kertis, et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
"An 8-NS 256K ECL SRAM With CMOS Memory Array and Battery Backup Capability", Hiep Van Tran et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
"A 7-NS 1-MB BICMOS ECL SRAM With Shift Redundancy", Atsushi Ohba et al, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.

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