Semiconductor memory device operable in burst mode and method of

Details Semiconductor memory device operable in burst mode and method of Semiconductor memory device operable in burst mode and method of

1997-01-30

1998-12-08

Nelms, David C.

Static information storage and retrieval

Addressing

Combined random and sequential addressing

395855, 39542107, G11C 800

Patent

active

058480234

ABSTRACT:
A circuit for generating memory cell array block selective signals which select memory cell array blocks included in a semiconductor memory device operable in burst mode, wherein the circuit is operated under the control of a burst mode control signal to generate memory cell array block selective signals sequentially and one by one through different and successive time cycles so that, according to the memory cell array block selective signals sequentially generated, the memory cell array blocks are also sequentially selected one by one through the different and successive time cycles for sequentially supplying a word line driver circuit with the memory cell array block selective signals one by one through the different and successive time cycles whereby memory cells included in different memory cell array blocks are sequentially selected one by one through the different and successive time cycles.

REFERENCES:
patent: 5327390 (1994-07-01), Takasugi
patent: 5559990 (1996-09-01), Cheng et al.
patent: 5634030 (1997-05-01), Nakano
patent: 5634139 (1997-05-01), Takita

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