Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2011-08-16
2011-08-16
Dinh, Son T (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S210130
Reexamination Certificate
active
08000123
ABSTRACT:
There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell; a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat.
REFERENCES:
patent: 5383159 (1995-01-01), Kubota
patent: 6160753 (2000-12-01), Shibayama
patent: 7051260 (2006-05-01), Ito et al.
patent: 06-103754 (1994-04-01), None
Noda Hiromasa
Okahiro Tetsuaki
Dinh Son T
Elpida Memory Inc.
Sughrue & Mion, PLLC
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