Semiconductor memory device of hierarchy word type and sub...

Details Semiconductor memory device of hierarchy word type and sub... Semiconductor memory device of hierarchy word type and sub...

2006-07-11

2006-07-11

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080

Reexamination Certificate

active

07075852

ABSTRACT:
In a sub word driver circuit in a semiconductor memory device of a hierarchy word structure using a main word line signal and a sub word line signal, a first NMOS transistor and a first PMOS transistor are connected in series. A second NMOS transistor is connected with a node between the first PMOS transistor and the first NMOS transistor. The source of the first PMOS transistor is connected with a sub word line inverted signal obtained by inverting the sub word line signal, and the source of the first NMOS transistor is connected with a first negative voltage. A single main word line signal is connected to a gate of the first PMOS transistor and a gate of the first NMOS transistor, and the sub word line signal is connected with a gate of the second NMOS transistor.

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