Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
1999-11-15
2002-03-26
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S669000, C438S740000, C438S624000
Reexamination Certificate
active
06362024
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device with a redundancy circuit having a fuse and a fuse cutting performance improved.
2. Description of the Related Art
In recent years, an element size becomes small with the high integration of a semiconductor memory device, and it is necessary to consider the relief of element fault. In a technique for the relief of such an element fault, a memory circuit and a redundancy circuit are previously formed and an element of the redundancy circuit is used in place of a fault element of the memory circuit. A fuse is used to switch from the memory circuit to the redundancy circuit.
FIGS. 4A
to
4
F are cross sectional views showing a method of manufacturing of a conventional semiconductor memory device in order of the process. An internal circuit of the conventional semiconductor memory device contains memory cells and fuses.
First, as shown in
FIG. 4A
, an element separation oxide film
101
, a word line
102
to function as the gate electrode of a memory cell transistor, a diffusion region
103
and a diffusion region
104
are formed on silicon substrate
100
so as to form a MOS transistor Q
1
. At this time, a large output MOS transistor Q
2
is also formed in alperipheral circuit (not shown). Moreover, a bit line
106
is formed of a film of tungsten silicide (WSi) on a lower interlayer insulating film
105
in such a manner that the bit line is connected with the diffusion region
103
of the MOS transistor Q
1
of the memory cell by a contact
107
. Fuses
108
are formed of a part of the WSi film. An interlayer insulating film is formed on the fuse
108
to cover the fuses
108
. An interlayer insulating film
109
is composed of the lower interlayer insulating film
105
and the interlayer insulating film to cover the fuses
108
Next, as shown in
FIG. 4B
, after forming a accumulation electrode
112
connected with the diffusion region
104
of the memory cell by a contact
111
and a capacitance insulating film
113
are formed, a counter electrode
114
is formed of a polysilicon film. Thus, a capacitor element C is formed. At this time, a part of the polysilicon film is also formed as an etching stopper film
115
in the region for a fuse cutting window to cover the fuses
108
.
Next, as shown in
FIG. 4C
, after a second interlayer insulating film
116
is formed on the polysilicon film
115
, the second interlayer insulating film
116
is selectively etched in the region for the fuse cutting window using the polysilicon film
115
as the etching stopper. Thus, an opening
125
is formed on the fuse.
Next, a first metal film is formed for the MOS transistor Q
2
of the peripheral circuit
2
(not shown). At this time, the first metal film is formed to cover the opening
125
, and is etched back. Thus, a first metal film
120
is formed to cover the inner side wall and peripheral portion of the opening. Subsequently, a portion of the polysilicon film
115
exposed in the bottom of the opening
125
is etched and removed using the first metal film
120
as a mask.
Next, as shown in
FIG. 4D
, the surface of the first metal film is flattened. That is, after a third interlayer insulating film
121
of a silicon oxide film is formed, an SOG film
122
is formed while a wafer is rotated. Then, project portions of the SOG film
122
are removed by a etching-back method or a CMP (chemical mechanical polishing) method. Thus, the surface of the first metal film is flattened. Moreover, a fourth interlayer insulating film
123
of a silicon oxide film is formed.
Next, as shown in
FIG. 4E
, a second metal film
126
is formed in the peripheral circuit (not shown). At the same time, a second metal film
127
is formed to have an opening in the opening
125
as shown in FIG.
4
E. Then, as shown in
FIG. 4F
, the fourth interlayer insulating film
123
, the SOG film
122
, and the third interlayer insulating film
121
are etched in order in the opening
125
such that only the first interlayer insulating film
109
remains directly on the fuses
108
in the opening
125
. Thus, the fuse cutting window
131
is formed where only the first interlayer insulating film
109
exists on the fuses
108
.
It should be noted that although the subsequent processes are omitted, a cover film and a protection film are formed of insulating films to cover the films such as the SOG film
122
exposed in the fuse cutting window
131
.
Therefore, in the fuse cutting window
131
formed in this way, the fuse
108
can be confirmed through the first interlayer insulating film
109
formed in the bottom of the fuse cutting window
131
, as shown in FIG.
1
. As shown in
FIG. 1
by a broken line arrow, if a laser beam LB is selectively irradiated to the fuse
108
through the first interlayer insulating film
109
, the fuse
108
is fused and cut by the energy of the laser beam LB. Through cutting of the fuse, the memory cell can be switched from the memory circuit to the redundancy circuit.
By the way, in the highly integrated DRAM in recent years, the memory cells and the fuses are highly integrated. When a plurality of fuses are arranged in parallel as described above, the array pitch is narrowed as small as about 2.5 &mgr;m. For this reason, when the fuse is fused and cut using the laser beam LB as described above, the laser beam must be irradiated to the fuse with a high resolution. However, in the conventional method of manufacturing the semiconductor memory device, it is difficult to form the insulating film which exists on the fuse, i.e., the first interlayer insulating film
109
to have a uniform film thickness. For this reason, as shown in
FIG. 1
, a part of the irradiated laser beam LB is reflected or scattered at the surface of the first interlayer insulating film
109
, so that the laser beam LB is irradiated to a fuse
108
A in the neighbor of the fuse
108
, too. Thus, not only the fuse
108
but also the fuse
108
A are fused and cut.
Also, because the film thickness of the first interlayer insulating film
109
remained on the fuse
108
(hereinafter, to be referred to as a remained film thickness) changes depending upon the place, the following problems would occur.
That is, first, the fuse
108
cannot be sometimes cut with a predetermined quantity of irradiation energy of the laser beam LB. For example, if the irradiation energy quantity of the laser beam LB is determined based on the small remained film thickness of the first interlayer insulating film
109
, the fuse
108
existing under the first interlayer insulating film
109
having the large remained film thickness cannot be fused and cut.
Second, there would be a case where the surface of the fuse
108
is made rough with the irradiation of predetermined laser beam LB or an element region under the fuse
108
receives any damage. For example, if the irradiation energy of laser beam LB is determined based on the large remained film thickness of the first interlayer insulating film
109
, the fuse
108
under the first interlayer insulating film
109
having the small remained film thickness is heated excessively, so that the fuse
108
A in the neighbor of the fuse
108
is also fused and cut. Also, the neighborhood of the fuse is burned to weaken the first interlayer insulating film so that moisture becomes easy to invade. Also, the laser beam reaches an element forming region directly below the fuse to give any damage so that leak current increases.
In this way, it is an important problem in the manufacturing process to make the remained film thickness uniform.
The existence of the SOG film could be considered as the reason why the first interlayer insulating film
109
on the fuse
108
cannot be made flat or uniform in thickness. That is, in the manufacturing process shown in
FIGS. 4A
to
4
F, the second interlayer insulating film
116
formed on the polysilicon film
115
is etched to form the opening
125
directly above the fuse
108
using polysilicon film
115
as the etching stopper. Subsequently, t
Iwasa Shinya
Kotou Makoto
Fourson George
Garcia Joannie Adelle
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