Semiconductor memory device layout including increased...

Details Semiconductor memory device layout including increased... Semiconductor memory device layout including increased...

2007-03-20

2007-03-20

Chowdhury, Tarifur (Department: 2112)

Static information storage and retrieval

Interconnection arrangements

C365S185120, C365S185130

Reexamination Certificate

active

11452798

ABSTRACT:
An integrated circuit memory device includes a memory cell array including first and second bit lines that extend side-by-side, a plurality of page buffers, a first isolation device electrically coupled to an end of the first bit line, and a second isolation device electrically coupled to an end of the second bit line. The second isolation device is arranged farther from the plurality of page buffers than the first isolation device. A first connection line is electrically coupled at a first end thereof to the first isolation device, and is electrically coupled at a second end thereof to one of the plurality of page buffers. A second connection line is electrically coupled at a first end thereof to the second isolation device, and is electrically coupled at a second end thereof to a farther one of the plurality of page buffers. The second connection line is arranged immediately adjacent to the first bit line.

REFERENCES:
patent: 5748531 (1998-05-01), Choi
patent: 6556508 (2003-04-01), Tsao et al.
patent: 6956767 (2005-10-01), Kang
patent: 100172422 (1998-10-01), None
patent: 1020030024223 (2003-03-01), None

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