Semiconductor memory device invalidating improper control...

Details Semiconductor memory device invalidating improper control... Semiconductor memory device invalidating improper control...

2006-08-15

2006-08-15

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S195000

Reexamination Certificate

active

07092314

ABSTRACT:
A control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit. Upon receiving a control command, the internal command generating circuit outputs an internal signal instructing an operation to access the memory cell at H level when a mask signal is at L level, while outputs an internal signal at L level when the mask signal is at H level, because a latch circuit is reset. The mask signal generating circuit outputs the mask signal at H level for a following cycle, when the internal signal is output at H level.

REFERENCES:
patent: 5815456 (1998-09-01), Rao
patent: 6246614 (2001-06-01), Ooishi
patent: 6466492 (2002-10-01), Ikeda

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