Semiconductor memory device integrating source-coupled-logic...

Details Semiconductor memory device integrating source-coupled-logic... Semiconductor memory device integrating source-coupled-logic...

2005-10-11

2005-10-11

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100, C365S230060, C365S230080, C365S227000, C365S189080, C365S189110, C365S194000, C326S098000, C326S095000, C326S115000, C326S108000, C326S106000

Reexamination Certificate

active

06954401

ABSTRACT:
It is an object of the invention to provide a circuit configuration wherein a decoder control signal Φ2is rendered unnecessary between an address buffer control signal Φ1and the decoder control signal Φ2, thereby implementing speed-up in operation of a decoder circuit. The object is attained by adoption of a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.

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patent: 2004/0160850 (2004-08-01), Son
patent: 2005/0063243 (2005-03-01), An
patent: 10-150358 (1998-06-01), None

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