Semiconductor memory device inputting/outputting data...

Details Semiconductor memory device inputting/outputting data... Semiconductor memory device inputting/outputting data...

2003-10-02

2004-10-05

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C341S101000

Reexamination Certificate

active

06801144

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-292408, filed Oct. 4, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device inputting/outputting data synchronously with a high-frequency clock signal.
2. Description of the Related Art
A circuit configuration of a general high-frequency clock signal synchronizing memory is shown in
FIG. 1. A
memory circuit
1
is roughly composed of a memory core section
2
and other I/F circuits.
The I/F circuits include right and left shift register sections
3
adjacent to the memory core section
2
, right and left I/O circuits (input/output circuits)
4
arranged between external signal lines corresponding to the shift register sections
3
and the shift register sections
3
, a DLL (Delayed Locked Loop) circuit
5
, and a control logic
6
.
The DLL circuit
5
generates a clock signal rclk controlling internal write data, synchronously with a write clock signal RXCLK which is input from outside, and also generates a clock signal tclk controlling internal read data, synchronously with a read clock signal TXCLK which is input from outside.
The control logic
6
performs a logic operation of a protocol which is input by an external command signal COMMAND and generates a control signal of the memory circuit
1
.
The right and left I/O circuits
4
input serial write data DQ<
8
:
15
> and DQ<
0
:
7
> from external input/output data lines, respectively, and output internal serial write data eWrite and oWrite that are input to the right and left shift register sections
3
comprising a plurality of shift registers, by using the internal write data control clock signal rclk.
In addition, the right and left I/O circuits
4
input internal serial read data eRead and oRead from the right and left shift register sections
3
, and output the serial read data DQ<
8
:
15
> and DQ<
0
:
7
> to the external input/output data lines, respectively, by using the internal read data control clock signal tclk.
<
0
:
7
> and <
8
:
15
> represent front 8-bit data and rear 8-bit data of totally 16-bit data, respectively. Letters “e” and “o” attached to Read and Write represent data of even numbers and data of odd numbers, respectively.
Each of the right and left shift register sections
3
inputs internal parallel read data RD<
0
:
7
> which is read from the memory core section
2
by the control signal during the read operation, and outputs internal parallel write data WD<
0
:
7
> by the control signal and writes the data to the memory core section
2
during the write operation.
Thus, the right and left shift register sections
3
, arranged between the right and left I/O circuits
4
and the memory core section
2
, convert the internal parallel read data RD<
0
:
7
> into the internal serial read data eRead and oRead during the read operation, and convert the internal serial write data eWrite and oWrite into the internal parallel write data WD<
0
:
7
> during the write operation.
The memory core section
2
is composed of a general DRAM circuit that consists of a row decoder, a column decoder, a memory cell array, a sense amplifier, a redundancy fuse and a DQ buffer.
FIG. 2
shows a path in which the parallel read data which is read from the memory core section
2
is converted into the serial read data, which reaches the I/O circuit
4
, in the layout of the conventional high-frequency clock signal synchronizing memory as described above.
The right and left I/O circuits
4
included in a peripheral circuit section
7
surrounded by a dotted line are divided into IO_
0
, IO_
1
, . . . IO_
7
and IO_
8
, IO_
9
, . . . IO_
15
, which are arranged on the right and left sides. Letters “_U” and “_B” attached to the serial read data eRead and oRead represent data which is read from the upper memory core sections
2
to the peripheral circuit section
7
and data which is read from the lower memory core sections
2
to the peripheral circuit section
7
, respectively. As the read data is read from either the upper memory core sections
2
or the lower memory core sections
2
in accordance with the address to which an access is made, the shift register section
3
outputs the serial read data eRead or oRead corresponding to the memory core section
2
to which an access is made.
When the data is written to the memory core sections
2
, the serial write data is input from the I/O circuits
4
to the shift register sections
3
. The shift register sections
3
convert the serial write data into the parallel write data, which is written to the memory core sections
2
.
Thus, as the data flow in the write operations can be obtained by reversing the data flow in the read operations, the path of the read data in the read operations is exemplified in FIG.
2
.
In the memory core sections
2
arranged on the upper and lower sides of the peripheral circuit section
7
, as shown in
FIG. 2
, 8-bit cell regions C
0
to C
7
are assigned to the left memory core sections
2
to correspond to the 8-bit IO_
0
to IO_
7
of the I/O circuit
4
, respectively. Similarly, 8-bit cell regions C
8
to C
15
are assigned to the memory core sections
2
of the right side to correspond to the 8-bit IO_
8
to IO_
15
, respectively. The high-frequency clock synchronizing memory is configured to have the input/output width of entirely 16 bits.
Thus, as shown in the memory core sections
2
of
FIG. 2
, the 8-bit regions C
0
to C
15
corresponding to the sequence of input/output to IO_
0
<
0
:
7
> to IO_
15
<
0
:
7
> are assigned to the memory cell arrays, respectively.
In active operations of the high-frequency clock signal synchronizing memory, two of the four memory core sections are selected, i.e., either a combination of the upper left and lower right memory core sections or a combination of the lower left and upper right memory core sections is selected, in accordance with the address signal.
The read data which is read in parallel for every 8 bits, from the memory core sections
2
to IO_
0
to IO_
15
, is converted into the 8-bit serial read data in the shift register sections
3
.
FIG. 3A
shows a configuration of the shift register section
3
. In the shift register section
3
, shift registers are arranged to correspond to the respective IO circuits IO_
0
to IO_
15
serving as the I/O circuit
4
. Each of the shift registers is configured to comprise write registers for the write operation and read registers for the read operation as shown in FIG.
3
B.
The write registers include write registers for even numbers which input the 4-bit serial write data eWrite corresponding to the data input to each IO at the time of even numbers and which output the 4-bit parallel write data WD <
0
,
2
,
4
,
6
>, and write registers for odd numbers which input the 4-bit serial write data oWrite corresponding to the data input to at the time of odd numbers and which output the 4-bit parallel write data WD <
1
,
3
,
5
,
7
>.
The read registers include read registers for even numbers which input the 4-bit parallel read data RD <
0
,
2
,
4
,
6
> corresponding to the data output from each IO at the time of even numbers and which output the 4-bit serial read data eRead, and read registers for odd numbers which input the 4-bit parallel read data RD <
1
,
3
,
5
,
7
> corresponding to the data output at times of odd numbers and which output the 4-bit serial read data oRead.
Specifically, the write registers and the read registers are operated synchronously with both edges of rise and fall of the write control clock signal rclk and the read control clock signal tclk, and perform 8-bit data transfer at a 4-cycle clock.
An example of the write operation and the read operation in the high-frequency clock signal synchronizing memory will be explained by using timing wavefor

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