Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-06-25
2004-08-31
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S189020
Reexamination Certificate
active
06785185
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device in which high-speed data transfer is carried out. The present invention also relates to an information apparatus using the semiconductor memory device and a method for determining an access period for the semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device, such as an EEPROM (flash memory), requires a much longer time for the writing of data than that for an SRAM (Static Random Access Memory) and a DRAM (Dynamic Random Access Memory). Conventionally, in order to accelerate the write speed of such a semiconductor memory device, data is first accumulated in a buffer region comprising of another type of memory element, such as an SRAM and the like, which are incorporated into the semiconductor memory device, and the accumulated data is then transferred together to the semiconductor memory device (an EEPROM, etc.).
This method has the following drawbacks. For example, the buffer region is used only for a buffering function and there is a large limitation when the buffer region is used for other purposes. Typically, since data to be written into the buffer region is deployed in another memory in advance, the efficiency of memory use is low.
To solve these drawbacks, the present inventors previously disclosed a semiconductor memory device in Japanese Patent Application No. 2000-176182, in which a high-speed writable memory is incorporated without a buffer and further in which a data transfer section is provided between the high-speed writable memory and a non-volatile semiconductor memory element, such as an EEPROM and the like, thereby making it possible to further improve write speed and the efficiency of memory use.
With such a device, data can be transferred from a RAM for use in normal tasks to an EEPROM or the like, thereby making it unnecessary for write data to be deployed into a different region in advance, or for an EEPROM or the like to be separately controlled so as to write data to a buffer. Use of an incorporated high-speed writable memory in tasks of a system or the like essentially requires a simultaneous execution of an external memory operation and a data transfer operation. To this end, as the high-speed writable memory, a dual port memory was preferably used.
However, the dual port memory has drawbacks, such as a large increase in cell area, a degradation in characteristics of memory elements, and the like. Further, an increase in memory capacity disadvantageously leads to an increase in cost, an increase in an area occupied by elements, a decrease in performance, and the like.
The term “external memory operation” as used herein indicates that a memory is operated by a command issued from outside of the memory so that data is input to the memory issued from out side of the memory or is output outside of the memory.
The term “externally” in “externally read”, “externally written”, “externally instructed”, and the like, as used herein indicates that such an operation is controlled by a command issued from outside so that data or instructions are transferred from or to outside of the memory.
FIG. 10
is a block diagram of an exemplary configuration of a conventional semiconductor memory device, showing major parts thereof. The semiconductor memory device carries out memory operations for a first conventional memory comprising of high write-speed memory elements and a second conventional memory comprising of low write-speed memory elements, and a data transfer operation which transfers data (the contents of the memory) between the memories. The semiconductor memory device will be described with reference to FIG.
10
. In the data transfer operation, data is mainly transferred from the high write-speed memory to the low write-speed memory. Reverse data transfer is also useful since the load of an external control device or the like can be reduced. There is substantially no difference in the data transfer operation between both directions. Here, only data transfer from the high write-speed memory to the low write-speed memory will be described.
As shown in
FIG. 10
, a semiconductor memory device
490
comprises: a control bus
401
and a data bus
402
externally connected: a switching circuit
410
(MUX
0
) for transferring information to each section in accordance with external control instructions; a write state machine (WSM)
460
for controlling data transfer operations and the like; a memory
430
(MEM
1
), such as an SRAM and the like, comprising of high-speed writable memory elements; a switching circuit
420
(MUX
1
) for switching between control of the memory
430
instructed by the WSM
460
and control of the memory
430
externally instructed; a memory
450
(MEM
2
), such as a flash memory and the like, comprising of rewritable memory elements; and a switching circuit
440
(MUX
2
) for switching between control of the memory
450
instructed by the WSM
460
and control of the memory
450
externally instructed.
Control information is externally input to the semiconductor memory device
490
through the control bus
401
and the data bus
402
including address buses. When the control information is intended for the memory
430
, the switching circuit
410
is used to transfer the control information via a control bus
411
and a data input/output bus
412
to the switching circuit
420
. When the control information is intended for the memory
450
, the control information is transferred via a control bus
413
and a data input/output bus
414
to the switching circuit
440
. Further, when the control information relates to a data transfer operation, the control information is transferred via a control bus
415
and a data input/output bus
416
to the WSM
460
.
It should be noted that a write operation to the memory
450
requires the WSM
460
when complicated control is necessary like writing to the EEPROM. In this case, the switching circuit
410
gives a rewrite instruction to the WSM
460
via the control bus
415
and the data bus
416
like a data transfer operation.
Next, a specific operation of the semiconductor memory device
490
will be described.
When data is externally read from the memory
430
, the switching circuit
410
is instructed via the control bus
401
to read data from the memory
430
. When control information received via the control bus
401
indicates a read operation from the memory
430
, the switching circuit
410
gives a read instruction to the switching circuit
420
via the control bus
411
, and the switching circuit
420
gives a read instruction to the memory
430
via a control bus
421
.
When the memory
430
is instructed via the control bus
421
to perform a read operation, the memory
430
reads data stored in designated memory elements, and outputs the data via a data bus
422
to the switching circuit
420
. The switching circuit
420
receives the data from the data bus
422
, and transfers the data via the data bus
412
to the switching circuit
410
.
The switching circuit
410
outputs the data received from the data bus
412
to outside of the memory device
490
via the data bus
402
. A series of the above-described operations allows external read out from the memory
430
.
Next, the case when data is externally written to the memory
430
will be described. A write instruction is transferred via the control bus
401
to the switching circuit
410
to the memory
430
. Data to be written is input via the data bus
402
to the switching circuit
410
.
When control information received via the control bus
401
is a write operation to the memory
430
, the switching circuit
410
gives a write instruction via the control bus
411
to the switching circuit
420
, and data to be written is input via the data bus
412
to the switching circuit
420
.
The switching circuit
420
gives a write instruction via the control bus
421
to the memory
430
, and inputs data to be written to the memory
430
via the data bus
422
.
When the memory
430
Fukui Haruyasu
Sumitani Ken
Le Thong Q.
Sharp Kabushiki Kaisha
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