Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
1999-12-17
2001-01-30
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Powering
Conservation of power
C365S226000, C365S042000, C365S189090, C365S189110
Reexamination Certificate
active
06181629
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device including a voltage generation circuit.
2. Description of the Background Art
Memories referred to as nonvolatile memories are known as one type of a semiconductor memory device. A flash memory is representative of such a nonvolatile memory that can program data electrically. In this flash memory, a constant high voltage is required at the time of programming and erasing. This high voltage is generated by boosting internally an externally applied power supply voltage in most cases. Control is provided so that a desired voltage is applied to the memory cell according to the operation mode.
For example, in a write operation, a write pulse apply period applying a write pulse corresponding to externally applied data, and a verify period to determine whether the threshold voltage of the memory cell has arrived at a desired level after the write pulse is applied to the memory cell are repeated alternately.
In the write pulse apply period, a charge pump circuit in the semiconductor memory device is rendered active, whereby a high voltage for writing is generated. The power consumption of the charge pump circuit during the boosting operation may become so great as to occupy a large ratio of the entire power consumption of the chip, which cannot be ignored.
For the purpose of reducing power consumption of the charge pump circuit, various measures have been taken such as reducing the number of stages forming the charge pump or employing mat division to reduce the load capacitance connected to the output of the charge pump circuit.
FIG. 11
is a circuit diagram showing a structure of a voltage generation circuit in a conventional semiconductor memory device.
Referring to
FIG. 11
, a voltage generation circuit
500
includes a positive voltage charge pump
502
activated in response to a charge pump activation signal PUMPE to boost an output potential Vout, a reset circuit
504
to set the level of output potential Vout to the level of a power supply potential Vcc according to a reset signal RSTE, and a decouple capacitor C
DEC
coupled between the output node of output potential Vout and the power supply node to which power supply potential Vcc is supplied. Since a circuit that becomes the load is connected between the output node of voltage generation circuit
500
and the ground node, a load capacitance C
LOAD
is depicted as the capacitance equivalent to this circuit.
FIG. 12
is an operation waveform diagram to describe the operation of voltage generation circuit
500
of FIG.
11
.
Referring to
FIGS. 11 and 12
, reset circuit
504
couples the output node of positive voltage charge pump
502
to power supply potential Vcc by reset signal RSTE before time t
1
. This state is referred to as “reset state”.
At time t
1
, reset signal RSTE is pulled down to an L level (logical low), and the reset state is canceled. At time t
2
, charge pump activation signal PUMPE is pulled up to an H level (logical high), whereby positive voltage charge pump
502
is rendered active. As a result, output potential Vout is gradually raised to a predetermined high potential. At the elapse of a rising time tr
1
from time t
2
, output potential Vout arrives at the level of a predetermined high potential VH.
Then, data is written.
Following a proper data write operation, positive voltage charge pump
502
is rendered inactive during the verify period in which determination is made whether the threshold voltage of the memory cell has arrived at a desired level or not. More specifically, at time t
3
, charge pump activation signal PUMPE is pulled down to an L level. At time t
4
, reset signal RSTE is pulled up to an H level, whereby the output node is coupled to power supply potential Vcc by reset circuit
504
. The charge accumulated in decouple capacitor C
DEC
and load capacitance C
LOAD
is discharged to the power supply node by reset circuit
504
.
When in the data writing operation or when data writing is insufficient, reset signal RSTE is canceled again at time t
5
. At time t
6
, charge pump activation signal PUMPE is rendered active again. Potential Vout attains the level of high potential VH at the elapse of a rising time tr
1
.
At time t
7
, charge pump activation signal PUMPE is rendered inactive. At time t
8
, reset signal RSTE is rendered active again to enter the verify period.
In the repetition of the boosting operation, the conventional boosting by a charge pump is initiated from the state where the output node is coupled to power supply potential Vcc by reset circuit
504
. Therefore, rising time tr
1
which is the period of time arriving at the level of high potential VH is equal to the case of boosting from the initial state, and is always constant. Power consumption of the charge pump circuit is greatest when output potential Vout is boosted from the level of power supply potential Vcc to high potential VH. A long period of time of this rise operation means that power consumption is increased accordingly. Also, it becomes a factor in inducing increase of the operation time required in data writing.
In the structure of the power supply including the charge pump circuit, control is provided so that the high potential generated at the charge pump circuit attains a predetermined constant potential by a detection circuit in order to apply a desired voltage to the memory cell. In general, a decouple capacitor C
DEC
is connected at the output node of the charge pump circuit in order to smooth the potential controlled by the detection circuit.
In the conventional circuit structure, the output node is reset every time the charge pump circuit is rendered inactive in the verify period, as described with reference to
FIGS. 11 and 12
. Therefore, the charge stored at decouple capacitor C
DEC
was discharged every time, inducing the problem of great power consumption.
SUMMARY OF THE INVENTION
An object of the present invention is to speed up the rising time of boosted potential to reduce power consumption and operation time.
According to an aspect of the present invention, a semiconductor memory device includes a potential generation circuit, a switch circuit, a potential stabilization circuit, and a storage unit.
The potential generation circuit applies a predetermined potential to an internal node. The switch circuit has one end connected to the internal node, and attains a conductive state when the potential generation circuit is rendered active, and attains a nonconductive state when the potential generation circuit is rendered inactive. The potential stabilization circuit is connected to the other end of the switch circuit to stabilize the potential of the internal node when the potential generation circuit is rendered active. The potential stabilization circuit maintains a predetermined potential when the potential generation circuit is rendered inactive. The storage unit receives the potential of the internal node to write data.
A main advantage of the present invention is that the potential stabilization circuit maintains the stored energy for reuse in the next voltage generation, so that the rising time can be shortened to reduce the operation time and power consumption.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5264743 (1993-11-01), Nakagome et al.
patent: 5347492 (1994-09-01), Horiguchi et al.
patent: 5394077 (1995-02-01), Atsumi
patent: 5394365 (1995-02-01), Tsukikawa
patent: 5526313 (1996-06-01), Itoh et al.
patent: 5544102 (1996-08-01), Tobita et al.
patent: 5561385 (1996-10-01), Choi
patent: 5805508 (1998-09-01), Tobita
patent: 6002354 (1999-12-01), Itoh et al.
patent: 6008690 (1999-12-01), Takeshima et al.
patent: 6031779 (2000-02-01), Takahashi et al.
patent: 409082917A (1997-03-01), None
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Viet Q.
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