Semiconductor memory device including two different...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S145000

Reexamination Certificate

active

07957193

ABSTRACT:
There are provided a first nonvolatile memory array including a plurality of nonvolatile memory elements which require an erase operation before a write operation, and a second nonvolatile memory array including a plurality of overwritable nonvolatile memory elements. A request to rewrite data is received by a control circuit. The control circuit writes data to be rewritten to the second nonvolatile memory array when the capacity of the data to be rewritten is not more than that of the second nonvolatile memory array.

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patent: 7773433 (2010-08-01), Garnier
patent: 7778078 (2010-08-01), Nagadomi et al.
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patent: 2008/0084782 (2008-04-01), Fukada
patent: 07-281842 (1995-10-01), None
patent: 2004-341989 (2004-12-01), None

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