Semiconductor memory device including MOS transistors each...

Details Semiconductor memory device including MOS transistors each... Semiconductor memory device including MOS transistors each...

2005-08-30

2005-08-30

Mai, Son (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C257S316000

Reexamination Certificate

active

06937514

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells, a memory cell array, bit lines, word lines, select gate lines, a column decoder, a first row decoder, a second row decoder, and first metal wiring. The memory cell includes a first MOS transistor with a charge accumulation layer and a control gate and a second MOS transistor connected to the first MOS transistor. The memory cell array has the memory cells arranged in a matrix. The word line connects commonly the control gates in the same row. The select gate line connects commonly the gates of the second MOS transistors in the same row. The first metal wiring layers are provided for every select gate lines, and pass through almost the central part of the memory cells. The first metal wiring layer is connected electrically to one of the select gate lines.

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W-H. Liu, et al., Non-Volatile Semiconductor Memory Workshop 4.1, pp. 1-3, “A 2-Transistor Source-Select (2TS) Flash EEPROM for 1.8V-Only Applications”, 1997.

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