Semiconductor memory device including memory cells connected to

Details Semiconductor memory device including memory cells connected to Semiconductor memory device including memory cells connected to

1996-12-31

2000-01-25

Mai, Son

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 506

Patent

active

RE0365319

ABSTRACT:
A memory cell array in a static random access memory (SRAM) includes an improved circuit. Memory cells in one row are connected to a ground line. The memory cells in another row are connected to the ground line. Word lines each are connected alternately to the memory cells of two rows column by column. In a read operation, when one of the word lines is activated, a current flows from the memory cell to the two ground lines. Since a total of currents flowing through one ground line is reduced, the rise of potentials of the ground lines is prevented, so that destruction of data can be prevented.

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D. Min et al. "Wordline Coupling Noise Reduction Techniques for Sealed DRAMs", 1990 Symposium on VLSI Circuits, Jun. 1990, pp. 81-82.

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