Semiconductor memory device including means for checking the ope

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371 671, G06F 1100, G06F 1130, G11C 2900

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active

054636353

ABSTRACT:
A data string representing the initial value (00000000) is supplied to an internal address generator. The internal address initial setting load signal is input to cause the internal address generator to be initialized. Then, a first detection signal is read out from the first detection circuit, and the level of the signal is checked. If the level of the first detection signal is HIGH, it indicates that the initialization of the internal address generator has been conducted normally. If the level of the first detection signal is LOW, it indicates that the initialization of the internal address generator has not been conducted normally. Thereafter, the count-up operation of the internal address generator is conducted while a count-up signal is supplied a predetermined number of times (255 times) to the internal address generator. A second detection signal is read out from a second detection circuit, and the level of the signal is checked. If the level of the second detection signal is HIGH, it indicates that the count-up operation of the internal address generator has normally been conducted. If the level of the second detection signal is LOW, it indicates that the count-up operation of the internal address generator has not been conducted normally.

REFERENCES:
patent: 4682328 (1987-07-01), Ramsay et al.
patent: 4773046 (1988-09-01), Akaogi et al.
patent: 4797886 (1989-01-01), Imada
patent: 5119380 (1992-06-01), Ohwada et al.
Alan Bentley, "Ram Tester Adapts to Memory Interface Requirements", Computer Design/Jun. 1979, pp. 124-136.
Rudy, "Memory Word Line Monitor", IBM Corp., 1976, p. 499.

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