Semiconductor memory device including junction field effect tran

Details Semiconductor memory device including junction field effect tran Semiconductor memory device including junction field effect tran

1991-11-06

1993-09-07

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

257266, 257296, 257306, 257390, 437 59, 437 28, 437228, 437911, 437919, H01L 2980, H01L 2170

Patent

active

052432092

ABSTRACT:
A dynamic random access memory includes a memory cell including a junction field effect transistor and a capacitor. A first conductivity-type semiconductor layer is formed on a main surface of a semiconductor substrate. The semiconductor layer includes a columnar part extending from the main surface of the semiconductor substrate and having a top surface and a sidewall surface. The junction field effect transistor is formed in the columnar part, and the capacitor is formed on the top surface of the columnar part. The junction field effect transistor includes a second conductivity-type impurity region and a gate electrode. The second conductivity-type impurity region is formed on the sidewall surface of the columnar part. The gate electrode is formed to surround the sidewall surface of the columnar part to be electrically in contact with the second conductivity-type impurity, region. The capacitor includes a storage node, a dielectric film, and a cell plate electrode. The storage node is formed to be electrically in contact with the top surface of the columnar part. The dielectric film is formed on the storage node. The cell plate electrode is formed on the dielectric film. It is possible to attain higher degree of integration and higher density of the memory cell without causing variation in the characteristics of the transistor included in the memory cell and without decreasing the noise margin of operation of the semiconductor substrate.

REFERENCES:
patent: 4417325 (1983-11-01), Harari
patent: 4423490 (1983-12-01), Roesner
patent: 4434433 (1984-02-01), Nishizawa
"A Reliable 1-Mbit DRAM with a Multiple-Bit-Test Mode", by Masaki Kumanoya et al., IEEE Journal of Solid State Circuits, vol. SC-20, No. 5, Oct. 1985, pp. 909-913.
"A Trench Transistor Cross-Point Dram Cell", by W. F. Richardson et al., IEDM Technical Digest, Dec. 1-4, 1985, pp. 714-717.

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