Semiconductor memory device including internal clock doubler

Details Semiconductor memory device including internal clock doubler Semiconductor memory device including internal clock doubler

2006-07-11

2006-07-11

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S191000, C365S194000, C365S230080

Reexamination Certificate

active

07075853

ABSTRACT:
A semiconductor memory device including an internal clock doubler including an internal clock doubler for doubling an external clock signal in a read mode to output a double clock signal in response to a plurality of external control signals, and delaying the external clock signal to output a clock control signal; a sense amplifier control signal generator for receiving the clock control signal and a standby signal of the plurality of external control signals signals which represents an output state of data to generate a plurality of sense amplifier control signals for controlling output of output data of a sense amplifier; a sense amplifier output unit for outputting output data of the sense amplifier in response to the plurality of sense amplifier control signals; and an output buffer unit for outputting output data of the sense amplifier synchronously with respect to the double clock signal in response to the standby signal when data are outputted.

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