Semiconductor memory device including gate electrode sandwiching

Details Semiconductor memory device including gate electrode sandwiching Semiconductor memory device including gate electrode sandwiching

1992-04-17

1994-07-19

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

257330, 257401, H01L 2978

Patent

active

053311973

ABSTRACT:
A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.

REFERENCES:
patent: 4979014 (1990-12-01), Hieda et al.
patent: 5019878 (1991-05-01), Yang et al.
patent: 5089870 (1992-02-01), Haond
patent: 5100827 (1992-03-01), Lylte
patent: 5115289 (1992-05-01), Hisamoto et al.
patent: 5163180 (1992-11-01), Eltoukhy et al.
IEDM Technical Digest, International Electron Devices Meeting, Washington, D.C., Dec. 1-4, 1985, "A New Programmable Cell Utilizing Insulator Breakdown", Sato et al., pp. 639-642.
IEDM Technical Digest, International Electron Devices Meeting, San Francisco, Calif., Dec. 11-14, 1988, "High Performance CMOS Surrounding Gate Transistor (SGT) For Ultra High Density LSIs", Takato et al., pp. 222-225.

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