Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-10-09
2007-10-09
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S189090, C365S189110, C365S204000, C365S226000
Reexamination Certificate
active
11087576
ABSTRACT:
A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects commonly the control gates of the first MOS transistors in a same row. The first charge pump circuit is activated and generates a first voltage in a write operation and erase operation. The first voltage is supplied with either the well region or the word lines. The discharge circuit, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage.
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Fujimoto Takuya
Hashiba Yoshiaki
Hirata Yoshiharu
Umezawa Akira
Kabushiki Kaisha Toshiba
Mai Son L.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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