Semiconductor memory device including dynamic type memory and st

Details Semiconductor memory device including dynamic type memory and st Semiconductor memory device including dynamic type memory and st

1998-01-14

2000-11-21

Hoang, Huan

Static information storage and retrieval

Addressing

Sync/clocking

365201, 36523003, 365222, 365195, G11C 800

Patent

active

061512699

ABSTRACT:
A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.

REFERENCES:
patent: 4608666 (1986-08-01), Uchida
patent: 4894770 (1990-01-01), Ward et al.
patent: 4926385 (1990-05-01), Fujishima et al.
patent: 5060196 (1991-10-01), Pae et al.
patent: 5175707 (1992-12-01), Murotani
patent: 5204837 (1993-04-01), Suwa et al.
patent: 5208779 (1993-05-01), Walther et al.
patent: 5226009 (1993-07-01), Arimoto
patent: 5353427 (1994-10-01), Fujishima et al.
patent: 5535174 (1996-07-01), Harston
patent: 5636176 (1997-06-01), Hashimoto et al.
"Writing a Port", Intel Corp.: Embedded Controller Handbook 1988, pp. 6-4, 6-5.
"Opening-Collector-Bus", Farber, G.: Bussysteme, 2nd edition, Munchen: R. Oldenbourg Verlag, 1987, pp. 36-37.
"Integrated Cached DRAM Lets Data Flow at 100 MHz", Dave Bursky, Electronic Design, Feb. 20, 1992, pp. 142, 144, and 146.
"A Circuit Design of Intelligent Cache DRAM with Automatic Write-Back Capability", Kazutami Arimoto et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 560-565.
"A 60-ns 3.3-V-Only 16-Mbit DRAM with Multipurpose Register", Kazutami Arimoto et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1184-1190.

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