Semiconductor memory device including divisional decoder circuit

Details Semiconductor memory device including divisional decoder circuit Semiconductor memory device including divisional decoder circuit

1996-08-02

1997-07-29

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 63, 36523001, G11C 800

Patent

active

056527314

ABSTRACT:
A semiconductor memory device includes a series circuit composed of a drive MOS transistor as a first MOS transistor and a reset MOS transistor as a second MOS transistor connected in series via a common connection node, a source of the reset MOS transistor being connected to a lower potential power supply, a main word line, and a sub-word line connected to the common connection node. An address signal includes a first part and a second part and a row address signal section decodes the first part of the address signal to generate a first row address signal and a second row address signal having a phase inverse to that of the first row address signal in accordance with the decoding result, and supplies the first row address signal to a drain of the drive MOS transistor and the second row address signal to a gate of a reset MOS transistor. A main decoder circuit decodes the second part of the address signal to output a main word line signal to the main word line in accordance with the decoding result before the row address signal section supplies the first and second row address signals. A third MOS transistor as a transfer section transfers the main word line signal to a gate of the drive MOS transistor. A fourth MOS transistor as a preventing section is provided to prevent the sub-word line from floating when there is no main word line signal and the source MOS transistor includes a gate connected to the first row address signal, a drain connected to the main word line, and a source connected to the common connection node.

REFERENCES:
patent: 4958326 (1990-09-01), Sakurai
patent: 5282175 (1994-01-01), Fujita et al.
patent: 5467032 (1995-11-01), Lee
patent: 5587959 (1996-12-01), Tsukude
patent: 5596542 (1997-01-01), Sugibayashi et al.
K. Noda et al, "A Boosted Dual Word-line Decoding Scheme for 256Mb DRAMs", 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 112 and 113.
R.D. Isaac et al., Nikkei Microdevices, Nov. 1993, pp. 38-45.
H.J. Yoo et al., "A 150MHz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods", 1995 IEEE International Solid-State Circuits Conference, Feb. 1995, pp. 250-251.

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