Semiconductor memory device including data bus pairs...

Details Semiconductor memory device including data bus pairs... Semiconductor memory device including data bus pairs...

2002-08-20

2004-03-09

Tran, Michael (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S201000

Reexamination Certificate

active

06704238

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a defect acceleration test by applying a voltage stress (also referred to as “a burn-in test” hereinafter) in a semiconductor memory device including data bus pairs respectively dedicated to data writing and data reading.
2. Description of the Background Art
To speed up data reading and writing operations, it is known to arrange data bus pairs formed with complementary data buses independently for data writing and data reading, respectively.
FIG. 5
is a circuit diagram showing a structure of conventional semiconductor memory device independently including a read data bus pair for data reading and a write data bus pair for data writing.
Referring to
FIG. 5
, conventional semiconductor memory device
2
includes at least one memory block MB having a plurality of memory cells MCs arranged in rows and columns. In each memory block MB, a plurality of word lines WLs are arranged corresponding to respective memory cell rows, and a plurality of bit line pairs BLPs are arranged corresponding to respective memory cell columns. Each bit line pair BLP has complementary bit lines BIT and /BIT. A structure of kth (k is a natural number) memory block MBk is representatively shown in FIG.
5
. In the memory block MBk, word lines WLk
1
-WLkm are arranged corresponding to respective m (m is a natural number) memory cell rows, and bit line pairs BLPk
1
-BLPkn are arranged corresponding to respective n (n is a natural number) memory cell columns. A bit line pair BLPk
1
is, for example, formed with complementary bit lines BITk
1
and /BITk
1
, and a bit line pair BLPkn is formed with complementary bit lines BITkn and /BITkn.
Semiconductor memory device
2
further includes a write data bus pair LWDBP and a read data bus pair LRDBP provided corresponding to each memory block MB, and a global write data bus pair GWDBP and a global read data bus pair GRDBP provided to a plurality of memory blocks MBs in common. A write data bus pair LWDBPk and a read data bus pair LRDBPk used to data reading and data writing for the memory block MBk are representatively shown in FIG.
5
. The write data bus pair LWDBPk is formed with complementary write data buses LWDBk and /LWDBk, and the read data bus pair LRDBPk is formed with complementary read data buses LRDBk and /LRDBk. Similarly, the global write data bus pair GWDBP is formed with complementary global write data buses GWDB and /GWDB, and the global read data bus pair GRDBP is formed with complementary read data buses GRDB and /GRDB.
Semiconductor memory device
2
further includes a plurality of bit line precharge and equalize circuits
10
, a plurality of read selection gates
20
, a plurality of write selection gates
30
, a write control circuit
40
, a sense amplifier circuit
50
, a read data bus drive circuit
60
, a read data bus precharge and equalize circuit
70
, a global read data bus precharge and equalize circuit
80
, and control circuits
500
,
510
.
Bit line precharge and equalize circuit
10
is provided corresponding to each memory cell column, and is activated in response to a block activation signal BACTk. More specifically, each bit line precharge and equalize circuit
10
isolates each of the complementary bit lines BIT and /BIT forming the corresponding bit line pair BLP from a bit line precharge voltage Vbp when the corresponding memory block MBk is selected to activate the block activation signal BACTk (to the H level) and a corresponding column selection signal Y
1
is also activated (to the H level). In the other periods, it electrically couples each of the corresponding bit lines BITk
1
and /BITk
1
to the bit line precharge voltage Vbp for precharging.
Read selection gate
20
is provided corresponding to each memory cell column, and is activated in response to a block read activation signal RBACTk. When activated, read selection gate
20
connects the bit line pair BLP of the corresponding memory cell column to the read data bus pair LRDBPk in response to the corresponding one of the column selection signals Y
1
-Yn. When inactivated, each read selection gate
20
disconnects the bit line pair BLP of the corresponding memory cell column from the read data bus pair LRDBPk, regardless of the corresponding column selection signal.
Write selection gate
30
is provided corresponding to each memory cell column, and is activated in response to a block write activation signal WBACTk. When activated, write selection gate
30
connects the bit line pair BLP of the corresponding memory cell column to the write data bus pair LWDBPk in response to the corresponding one of the column selection signals Y
1
-Yn. When inactivated, each write selection gate
30
disconnects the bit line pair BLP of the corresponding memory cell column from the write data bus pair LWDBPk, regardless of the corresponding column selection signal.
Write control circuit
40
is activated in response to the block write activation signal WBACTk. When activated, it sets the voltages of the write data buses LWDB and /LWDB corresponding to the voltages of the global write data buses GWDB and /GWDB which transfer the write data.
Sense amplifier circuit
50
is activated in response to a block sense enable signal BSSEk. When activated, it amplifies a voltage difference between the read data buses LRDBk and LRDBk.
Read data bus drive circuit
60
drives the voltages of the global read data buses GRDB and /GRDB such that, the voltage difference corresponding to that between the read data buses LRDBk and /LRDBk is generated between the global read data buses GRDB and /GRDB.
Read data bus precharge and equalize circuit
70
is provided corresponding to the read data bus pair LRDBPk, and is activated in response to a local precharge signal /LDPCHk. When activated, read data bus precharge and equalize circuit
70
sets each of the corresponding read data buses LRDBk and /LRDBk to the precharge voltage (for example, a power supply voltage Vcc). When inactivated, it isolates each of the corresponding read data buses LRDBk and /LRDBk from the precharge voltage.
Though bit line precharge and equalize circuit
10
, the plurality of read selection gates
20
, the plurality of write selection gates
30
, write control circuit
40
, sense amplifier circuit
50
, read data bus drive circuit
60
, and read data bus precharge and equalize circuit
70
corresponding to the memory block MBk are representatively shown in
FIG. 5
, such circuit group is similarly provided to each memory block.
Global read data bus precharge and equalize circuit
80
is activated in response to a global precharge signal /GDPCH. When activated, it sets each of the global read data buses GRDB and /GRDB to the precharge voltage (for example, the power supply voltage Vcc). When inactivated, it isolates each of the global read data buses GRDB and /GRDB from the precharge voltage.
The structure of the control circuit will be described in the following. Hereinafter, a high voltage state (the high level) and a low voltage state (the low level) of each signal line, signal or data having binary levels will simply be referred to as “the H level” and “the L level”.
Control circuit
500
generates a read activation signal RACT and a sense enable signal SE which are activated in data reading. Control circuit
500
includes an internal clock signal intCLK, a logic gate
502
outputting an NAND logical operation result with a read cycle signal RE which is set to the H level in data reading, an inverter
504
inverting the output of logic gate
502
, and a delay circuit
506
delaying the output of inverter
504
. The output of inverter
504
is provided as the read activation signal RACT to control circuit
510
. The output of delay circuit
506
is provided as the sense enable signal SE to control circuit
510
.
Control circuit
510
controls the activation of bit line precharge and equalize circuit
10
, read selection gate
20
, write selection gate
30
, write control circuit

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