Semiconductor memory device including charge storage layer...

Details Semiconductor memory device including charge storage layer... Semiconductor memory device including charge storage layer...

2009-09-21

2011-11-08

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185210, C365S185230, C365S185010, C365S185120, C365S185260

Reexamination Certificate

active

08054683

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells, signal lines, and a control unit. Each of the plurality of memory cells includes a charge storage layer. Each of the plurality of memory cells includes a control gate and is configured to hold two-or-higher-level data. Each of signal lines is electrically connected with a gate or one end of a current path of each of the memory cells. Each of signal lines has a line width which differs depending on each interval between the memory cells adjacent to each other. The control unit controls a voltage applied to each of the signal lines in accordance with the line width of each of the signal lines.

REFERENCES:
patent: 7443757 (2008-10-01), Cernea et al.
patent: 2006/0244013 (2006-11-01), Matsunaga et al.
patent: 2008/0205163 (2008-08-01), Park et al.
patent: 2009/0067236 (2009-03-01), Isobe et al.
patent: 2002-280388 (2002-09-01), None
U.S. Appl. No. 12/885,066, filed Sep. 17, 2010, Shiino, et al.

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