Semiconductor memory device including address transition detecto

Details Semiconductor memory device including address transition detecto Semiconductor memory device including address transition detecto

1993-09-27

1995-05-09

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365191, 365233, G11C 700

Patent

active

054146720

ABSTRACT:
A dynamic random access memory (DRAM) includes an improved column system enable circuit. The circuit provides a column system enable signal /CE in response to an externally applied timing control signal Stc. An ATD detects transition of an address signal after being activated in response to the signal /CE. Since an activation timing of ATD can be determined by an external signal, it is possible to test easily an address transition detecting operation immediately after activation of ATD. Therefore, it is possible to shorten time required for the test.

REFERENCES:
patent: 5214610 (1993-05-01), Houston
patent: 5243575 (1993-09-01), Sambandan et al.
patent: 5301165 (1994-11-01), Ciraula et al.
patent: 5305283 (1994-04-01), Shimokura et al.
patent: 5307324 (1994-04-01), Nishimoto
patent: 5335206 (1994-08-01), Kawamoto
"A 1Mb CMOS DRAM with Fast Page and Static Column Modes", by Shozo Saito et al, Digest of Technical Papers, 1985 IEEE, pp. 252-253.

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