Semiconductor memory device including a word line driving circui

Static information storage and retrieval – Addressing – Plural blocks or banks

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36523004, 36523006, G11C 800

Patent

active

055174566

ABSTRACT:
A memory cell array is divided into a plurality of blocks selected by an upper row address and further divided into a plurality of sub blocks in a word line direction. Word line driving circuits are provided individually for each of the sub blocks. Further, a plurality of word line driving current supplying circuits are provided which are selectively activated in response to an input of all or part of an upper row address for selection of one of the plurality of blocks to supply word line driving current to the word line driving circuits. The word line driving circuits in the same column direction are supplied with word line driving current by way of at least two signal lines.

REFERENCES:
patent: 5327389 (1994-07-01), Seok et al.

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