Semiconductor memory device including a redundant circuit

Details Semiconductor memory device including a redundant circuit Semiconductor memory device including a redundant circuit

1998-09-10

1999-08-10

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257203, 365200, 365202, 365225, 36523003, 36523004, H01L 2710

Patent

active

059362693

ABSTRACT:
An address program circuit 11 provided in a semiconductor memory device receives an internal address signal which corresponds to an address signal, and outputs a signal /RE1 for causing the switching operation from a defective memory cell to a redundant memory cell. One fuse of each pair of fuses F10-1 and F10-2, F11-1 and F11-2, . . . , F1n-1 and F1n-2 in each of selection portions S0, S1, . . . Sn is cut off in response to the address of the defective memory cell, thereby the signal /RE1 being made active upon receipt of a predetermined internal address signal. With this structure, the defective memory cell may be remedied without generating any complementary internal address corresponding to the address signal as inputted externally.

REFERENCES:
patent: 5787043 (1998-07-01), Akioka et al.
patent: 5793683 (1998-08-01), Evans
patent: 5841707 (1998-11-01), McClure
patent: 5841708 (1998-11-01), Nagata

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