Semiconductor memory device including a plurality of memory...

Details Semiconductor memory device including a plurality of memory... Semiconductor memory device including a plurality of memory...

2001-06-11

2002-06-11

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S063000

Reexamination Certificate

active

06404695

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a plurality of memory blocks arranged in a matrix of rows and columns and enabling simultaneous input/output of a plurality of pieces of data.
2. Description of the Background Art
FIG. 15
is a block diagram showing a configuration of a conventional dynamic random access memory (hereinafter referred to as DRAM) used as a memory to be mounted together with a logic circuit. In
FIG. 15
, the DRAM includes sixteen memory blocks MB arranged in four rows and four columns. The sixteen memory blocks MB are separated and enclosed by five sense amplifier zones
71
and five sub decoder zones
72
.
A main row decoder MRD is provided at one end of each row of memory blocks MB. A number of sub row decoders (not shown) are dispersedly arranged at each sub decoder zone
72
. Each sense amplifier zone
71
is provided with eight column selecting lines CSL
0
to CSL
7
and also with a number of sense amplifiers (not shown) that are dispersedly arranged. One end of each of the eight column selecting lines CSL
0
to CSL
7
is connected to a column decoder CD. A data input/output line pair group
73
is provided corresponding to each column of memory blocks MB. One end of each data input/output line pair group
73
is connected to a write/read circuit
74
.
Four main row decoders MRD and sub decoders select, for example, one memory block MB row and one word line of each memory block MB in the selected row, and activate a plurality of memory cells corresponding to the selected word line. Further, one column selecting line is selected from sixteen column selecting lines CSL
0
to CSL
7
and CSL
0
to CSL
7
arranged at either side of the selected memory block MB row by column decoders CD, and a plurality of memory cells corresponding to the selected column selecting line among the activated plurality of memory cells in each memory block MB are connected to write/read circuit
74
via data input/output line pair group
73
. Write/read circuit
74
performs writing/reading of data in each of the activated memory cells via each data input/output line pair group
73
. The DRAM enables simultaneous input/output of multiple pieces of data.
However, such a DRAM has a problem in that longer line-routing and larger capacitance value of column selecting lines CSL
0
to CSL
7
would deaden a waveform of an output signal of column decoder CD, making faster column selecting operation difficult.
FIG. 16
is a block diagram showing a configuration of another conventional DRAM. The DRAM in
FIG. 16
is different from the DRAM in
FIG. 15
in that eight sub column selecting lines SCSL
0
to SCSL
7
and a repeater RP are added corresponding to each memory block MB in each sense amplifier zone
71
. Repeater RP changes the level of sub column selecting lines SCSL
0
to SCSL
7
in response to that the level of sub column selecting lines SCSL
0
to SCSL
7
has exceeded a predetermined threshold potential. A plurality of memory cells, corresponding to the sub column selecting lines that are set to be at a selected level, of a plurality of activated memory cells in each memory block MB are connected to write/read circuit
74
via a data input/output line pair group (not shown). In this DRAM, a waveform of an output signal of column decoder CD can be regenerated by repeater RP, so that faster column selecting operation is enabled.
However, the DRAM in
FIG. 16
has a problem in that eight sub column selecting lines SCSL
0
to SCSL
7
must be arranged in parallel with eight column selecting lines CSL
0
to CSL
7
in each sense amplifier zone
71
, increasing the area of sense amplifier zone
71
.
SUMMARY OF THE INVENTION
Therefore, a main object of the present invention is to provide a semiconductor memory device having a small area of a first zonal region and a fast operation speed.
In a semiconductor memory device according to the present invention, a column selecting circuit includes a plurality of first signal transmission lines provided corresponding to each memory block row and arranged to extend along the length of a first zonal region adjacent to a corresponding memory block row; a plurality of second signal transmission lines provided corresponding to each memory block column and arranged to extend along the length of a second zonal region adjacent to a corresponding memory block column; a first decoder provided corresponding to each memory block row and generating a first predecode signal based on a column address signal to apply the first predecode signal to a plurality of corresponding first signal transmission lines; a second decoder provided corresponding to each memory block column and generating a second predecode signal based on the column address signal to apply the second predecode signal to a plurality of corresponding second signal transmission lines; and a third decoder provided corresponding to each memory block and arranged at a crossing portion of the first and second zonal regions adjacent to a corresponding memory block, and selecting one bit line pair from a plurality of bit line pairs of the corresponding memory block based on the first predecode signal from the plurality of corresponding first signal transmission lines and the second predecode signal from the plurality of corresponding second signal transmission lines. Therefore, the area of the first zonal region may be smaller compared to that of a conventional memory device in which a plurality of signal transmission lines for column selection were provided only in the first zonal region. Further, the third decoder provided at the crossing portion of the first and second zonal regions selects a bit line pair of a memory block in the vicinity of the third decoder, so that the speed of the column selecting operation can be increased.
Preferably, the first predecode signal includes a plurality of first signals respectively applied to the plurality of first signal transmission lines, and the second predecode signal includes a plurality of second signals respectively applied to the plurality of second signal transmission lines. One first signal of the plurality of first signals is set to be at an activated level by the first decoder and one signal of the plurality of second signals is set to be at the activated level. This can make the number of the signal transmission lines smaller.
More preferably, the third decoder includes a plurality of logic circuits respectively provided corresponding to the plurality of column selecting lines and arranged at a plurality of crossing portions of the plurality of first signal transmission lines and the plurality of second signal transmission lines, each of the plurality of logic circuits setting a corresponding column selecting line to be at a selected level in response to that a first signal from a corresponding first signal transmission line and a second signal from a corresponding second signal transmission line are both set to be at the activated level. When the column selecting line is set to be at a selected level, a column selection gate between a bit line pair and a write/read circuit corresponding to the column selecting line is made conductive. This facilitates configuration of the third decoder.
More preferably, the plurality of first signal transmission lines are paired up to constitute a plurality of first signal transmission line pairs; the plurality of second signal transmission lines are paired up to constitute a plurality of second signal transmission line pairs; the first predecode signal includes a plurality of sets of first signals and complementary signals of the first signals respectively applied to the plurality of first signal transmission lines; and the second predecode signal includes a plurality of sets of second signals and complementary signals of the second signals respectively applied to the plurality of second signal transmission lines. One set of a first signal and its complementary signal o

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