Semiconductor memory device including a plurality of dynamic mem

Details Semiconductor memory device including a plurality of dynamic mem Semiconductor memory device including a plurality of dynamic mem

1996-11-07

1998-11-03

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

365 63, G11C 800

Patent

active

058319280

ABSTRACT:
A semiconductor device includes a memory cell array having memory cells arranged in a matrix form, a plurality of bit lines for communicating information to the memory cells, and a plurality of word lines crossing the bit lines to select among the memory cells, a plurality of sense amplifiers for amplifying data read out onto the bit lines, a plurality of data lines for transferring data amplified by the sense amplifiers to the outside of the cell array, the plurality of data lines including first and second wiring layers, a plurality of column select circuits for controlling connections of the plurality of data lines and the plurality of sense amplifiers, and a plurality of control signal lines connected to the plurality of column select circuits, the plurality of control lines including third and fourth wiring layers.

REFERENCES:
patent: 5293348 (1994-03-01), Abe
patent: 5341341 (1994-08-01), Fukuzo
patent: 5392242 (1995-02-01), Koike
Y. Watanabe, et al. "A 286mm.sup.2 256Mb DRAM with X32 Both-Ends DQ", 1995 Symposium on VLSI Circuits Digest of Technical Papers, (pp. 105-106), Jun. 1995.

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