Semiconductor memory device including a column decoder array

Static information storage and retrieval – Addressing – Plural blocks or banks

Reexamination Certificate

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Details

C365S230080, C365S230060, C365S189190, C365S189140

Reexamination Certificate

active

07630271

ABSTRACT:
A semiconductor memory device is presented that exhibits an enhanced read/write data retrieval efficiency brought about in part by a uniquely shared column array communication scheme. The semiconductor memory device includes: at least one group of banks, the banks being disposed adjacent to each other to form a radially symmetrical arrangement of banks having a row and column geometry; and a column decoder array is positioned between pairs of vertically disposed banks in which the column decoder array communicates with this pair of vertically disposed banks so that a single column select signal from the column decoder array can be used to select a given memory cell of the one bank of this vertically disposed banks.

REFERENCES:
patent: 2003/0223262 (2003-12-01), Fujisawa
patent: 2004/0004890 (2004-01-01), Fujisawa et al.
patent: 2004/0264260 (2004-12-01), Kono
patent: 2005/0259499 (2005-11-01), Kim et al.
patent: 2006/0098515 (2006-05-01), Mochida
patent: 2007/0162685 (2007-07-01), Suh
patent: 1994-0002858 (1994-02-01), None
patent: 1020010047329 (2001-06-01), None
patent: 1020060027665 (2006-03-01), None

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