Semiconductor memory device including a boost potential generati

Details Semiconductor memory device including a boost potential generati Semiconductor memory device including a boost potential generati

1994-12-27

1996-12-24

Zarabian, A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365222, G11C 800

Patent

active

055879586

ABSTRACT:
A semiconductor integrated circuit device includes a boost potential generation circuit, word line drive system circuit, refresh cycle select circuit, word line system boost potential generation circuit and boost potential generation system control circuit. The boost potential generation circuit steadily generates a higher boost potential than an externally applied voltage. The word line drive system circuit delivers the boost potential, as a power supply, from the boost potential generation circuit so as to drive the corresponding word line. The word line system boost potential control circuit sets at a substantially constant level a boost potential output from the boost potential generation circuit. The boost potential generation system control circuit receives a designation signal from the refresh cycle select circuit so as to designate a refresh cycle and supplies a control signal, which is generated based on the designation signal, to the boost potential generation circuit, whereby, when more word lines are driven at a time by the word line system drive circuit, a current supply capability of the boost potential generation circuit is increased and, when less word lines are driven at a time, the current supply capability of the boost potential generation circuit is decreased.

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Horiguchi et al., "A Tunable CMOS-DRAM Voltage Limiter with Stabilized Feedback Amplifier", IEEE Journal of Solid-State Circuits, Oct. 1990, No. 5, New York, pp. 1129-1134.
Publication, "A 1.5V Circuit Technology for 64Mb DRAMs", Y. Nakagome et al., 1990 Symposium on VLSI Circuits, pp. 17-18.

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