Semiconductor memory device in which use of cache can be...

Details Semiconductor memory device in which use of cache can be... Semiconductor memory device in which use of cache can be...

2000-05-11

2002-04-30

Kim, Hong (Department: 2186)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189011, C711S104000

Reexamination Certificate

active

06381190

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing system using a semiconductor device, and more particularly to a semiconductor memory device in which use of a cache memory can be selected and a data processing system using the semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device with a cache memory as well as memory cells is conventionally known, as shown in FIG.
1
. In such a conventional semiconductor memory device, for example, a data is read out from the memory cells of a memory cell array
101
in a Bank A to a sense amplifier section
102
and sensed. The sense data are transferred to one of cache memories
103
such as channel memories. The cache memory
103
is a register array as a channel constituted by SRAMs (static random access memory). The stored data are read out from the cache memory
103
, and are then outputted as a read data from an input/output circuit
106
via a data control circuit
104
and a latch circuit
105
. On the other hand, write data are inputted into the input/output circuit
106
, and is then written into one of the cache memories
103
via the latch control circuit
105
and the data control circuit
104
. Then, the write data are transferred from the cache memory
103
to the sense amplifier section
102
. Finally, the write data are stored in memory cells of the memory cell array.
In the conventional semiconductor memory device, when the data are read out from the memory cells
101
and also the data are written into the memory cells
101
, the data are temporarily stored in one of the cache memories
103
. As a consequence, the data transfer speed executed via the cache memory
103
would be strongly restricted depending on the cache memory
103
.
In conjunction with the above description, an input/output control system is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-161932). In this reference, a digital data processor is composed of two functional units and a controller, and data are transferred between them. Each functional unit has a related memory element such as a random access main memory. A first functional unit is composed of a transmission element (sender) which generates a message descriptor block (MDB) transmission signal which specifies one or more addresses to the related memory to which data should be transferred. The controller distinguishes the MDB transmission signal which matches with a selected MDB reception signal and generates a signal to carry out a data transfer between the corresponding memory positions of the first and second functional units which are specified based on the matched MDB signal. Thus, the improvement in the data transfer efficiency between the digital data processing functional units is aimed.
Also, a computer system using a bus bridge is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-237223). In this reference, a read request is outputted from a bus master unit to a main memory
5
via a second bus
8
. At this time, when it is informed by a cache test section
10
that a cache write back is necessary, a cache write back data is written from a write back control section
12
back to the main memory unit
5
via a main memory control unit
21
. At the same time, the cache write back data is also transferred to a data by-pass section
22
. The data for the read request is taken directly into a second bus control section
9
via the by-pass section
22
and transferred to a bus master unit via the IO bus
8
. Thus, a data read from the main memory unit
5
is avoided.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor memory device with a cache memory in which a data can be read out from and written in a memory cell without passing through the cache memory.
Another object of the present invention is to provide a semiconductor memory device in which a restriction of data transfer speed due to a cache memory can be released.
Still another object of the present invention is to provide a semiconductor memory device in which a memory cell array can be accessed without passing through a cache memory when a row address continuously changes.
Yet still another object of the present invention is to provide a data processing system using the semiconductor memory device in either of the above.
In order to achieve an aspect of the present invention, a semiconductor memory device, includes a plurality of banks, each of which includes a memory cell array and a sense amplifier section, a plurality of channel memories, a data control circuit, a first bus provided between the plurality of banks and the plurality of channel memories, a second bus provided between the plurality of channel memories and the data control circuit, and a third bus between the plurality of banks and the data control circuit. The data control circuit outputs write data to the sense amplifier section of a specified one of the plurality of banks via the third bus in a direct write access mode, and inputs read data from the sense amplifier section of a specified one of the plurality of banks via the third bus in a direct read access mode. Also, the data control circuit outputs write data to the sense amplifier section of a specified one of the plurality of banks via the second bus, a specified one of the plurality of channel memories and the first bus in an indirect write access mode, and inputs read data from the sense amplifier section of a specified one of the plurality of banks via the first bus, a specified one of the plurality of channel memories and the second bus in an indirect read access mode.
Here, each of the first to third buses includes a bus driver. At this time, the bus drivers of the first and second buses may be set to an enable state in the indirect write access mode and the indirect read access mode, and may be set to a disable state in the direct write access mode and the direct read access mode. Also, the bus driver of the third bus may be set to an enable state in the direct write access mode and the direct read access mode, and may be set to a enable state in the indirect write access mode and the indirect read access mode. In this case, the data control circuit may include a flag used to specify one of an indirect access mode and a direct access mode based on an access mode specify internal command. The indirect access mode includes the indirect write access mode and the indirect read access mode, and the direct access mode includes the direct write access mode and the direct read access mode.
Also, the semiconductor memory device may further include an internal command generating section generating the access mode specify internal command based on a signal supplied to a first specific external input terminal. In this case, the internal command generating section may generate an operation mode specify internal command based on signals supplied to second specific external input terminals to set one of a write mode and a read mode.
Alternately, the semiconductor memory device may further include an internal command generating section generating the access mode specify internal command based on signals supplied to specific external input terminals.
In order to achieve another aspect of the present invention, a method of accessing a semiconductor memory device, is attained by setting a direct write access mode in response to a direct access internal command and a write internal command; by setting a direct read access mode in response to the direct access internal command and a read internal command; by setting an indirect write access mode in response to an indirect access internal command and the write internal command; by setting an indirect read access mode in response to the indirect access internal command and the read internal command; by accessing a specific memory cell array such that write data externally supplied is written into the specific memory cell array via a data control circuit, a first bus and a sense amplifier section fo

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