Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-06-07
2003-05-20
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S230030, C365S185140, C365S185240
Reexamination Certificate
active
06567305
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-173716, filed Jun. 9, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a non-volatile semiconductor memory device such as a NAND cell, a NOR cell, a DINOR Cell, AND cell type EEPROM or the like.
Conventionally, as one semiconductor memory device, there is known an electrically rewritable EEPROM. Among such EEPROM'S, a NAND cell type EEPROM which constitutes a NAND cell block by connecting in series a plurality of memory cells is noted as a type of EEPROM which enables a high degree of integration,
One memory cell in the NAND cell type EEPROM has a FET-MOS structure in which a floating gate (charge storage layer) and a control gate are stacked on the semiconductor substrate via an insulating film. Then, a plurality of memory cells arranged adjacent to each other are connected in series in the form of shared sources and drains to constitute a NAND cell and the memory cells are connected to a bit line as one unit. Such NAND cells are arranged in a matrix to constitute a memory cell array. Memory cell arrays are integrated and formed on a p-type semiconductor substrate or in a p-type well region.
The drain on one end side of the NAND cell arranged in a column direction of the memory cell array is commonly connected to the bit line via a select gate transistor while the source on the other end side is connected to a common source line via the select gate transistor as well. A control gate of the memory transistor and a gate electrode of the select gate transistor are connected in common as the control gate line (word line) and the select gate line respectively in a row direction of the memory cell arrays.
This NAND cell type EEPROM operates in a manner as described below. An operation of programming data is conducted in order, primarily starting from a memory cell disposed at a location most remote from a bit line contact. In the beginning, when the operation of programming data is started, 0V (“1” data writing bit line) or a power supply voltage Vcc (“0” data writing bit line) is given to the bit line in accordance with the data to be written while Vcc is given to the select gate line on the side of the selected bit line contact. In this case, in the selected NAND cell connected to the “1” data writing bit line, a channel portion in the NAND cell is fixed to 0V via the selected gate transistor. On the other hand, in the selected NAND cell connected to the “0” data writing bit line, the channel portion in the NAND cell is charged to [Vcc−Vtsg] (however, Vtsg denotes a threshold voltage) via the select gate transistor followed by being set to a floating state. After that, the control gate line of the select memory cell in the select NAND cell is set to 0V→Vpp (=about 20V: a programming high voltage) while the other control gate line in the select NAND cell is set to 0V→Vmg (=about 10V: an intermediate voltage).
Since the channel portion in the NAND cell is fixed to 0V in the select NAND cell connected to the “1” data writing bit line, a large potential difference (about 20V) is generated between the control gate line (=Vpp potential) of the select memory cell in the select NAND cell and the channel portion (=0V), and the injection of electrons is generated from the channel portion to the floating gate. As a consequence, the threshold voltage of the selected memory cell is shifted in a positive direction to complete the “1” data writing.
In contrast, since the channel portion in the NAND is set to the floating state in the select NAND cell connected to the “0” data writing bit line, the potential of the channel portion rises to the [Vcc−Vtsg] potential→Vmch (=about 8V) while maintaining the floating state along with a rise in the voltage of the control gate line (0V→Vpp, Vmg) under the influence of the capacity coupling between the control gate line and the channel portion in the select NAND cell. At this time, since the potential difference between the control gate line (Vpp potential) of the select memory cell in the select NAND cell and the channel portion (=Vmch) is set to a relatively small level of about 12V, no injection of electrons is generated. Consequently, the threshold voltage of the select memory cell does not change and is maintained in a negative state.
Data is erased simultaneously with respect to all the memory cells in the select NAND cell block. That is, all the control gate lines in the select NAND cell are set to 0V to apply a high voltage of about 20V to the bit line, the source line, the p-type well region (or the p-type semiconductor substrate), the control gate line in the non-select NAND cell block and all the select gate lines. Consequently, electrons in the floating gate are emitted to the p-type well region (or the p-type semiconductor substrate) in all the memory cells in the select NAND cell block so that the threshold voltage is shifted in a negative direction.
On the other hand, the operation of reading data is conducted by setting the control gate line of the selected memory cell to 0V, setting the control gate and the selected gate line of the other memory cell to the power supply voltage Vcc and detecting whether or not current flows in the select memory cell.
As is apparent from the above explanation on the operation, in the NAND cell type EEPROM, the channel in the select NAND cell connected to the “0” data writing bit line is set to the floating state having a Vmch potential by using a capacity coupling with the control gate line at the time of the data programming operation. When a leakage current to the source line via the select gate transistor on the source line side is large, the channel potential in the floating state is largely decreased, and the potential difference between the control gate and the channel of the select memory cell is increased. Thus, the possibility is increased that the injection of electrons from the channel to the floating gate is generated. That is, the possibility is increased in that “1” data is erroneously written (hereinafter referred to as an error programming operation). Then, a technique for biasing a source line to a positive voltage of about Vcc is normally used at the time of a data programming operation in order to decrease the above leakage current.
By the way, in such NAND cell type EEPROMs, it is thought that a method is required for shortening the time required for programming and erasing data in all the memory cells in the chip by using an operation in which the number of memory cells in which “1” data is written at one time is larger than the normal data programming operation, in order to realize a decrease in the test cost as a result of shortening the time required for quality control testing such as in normal data programming and data erasing testing. For example, a mode for programming “1” data in one package in a plurality of blocks is provided for programming “1” data into a larger number of memory cells at one time than at the time of a normal data programming operation. Naturally, in the mode for programming “1” data into a plurality of blocks in a package, in a larger number of NAND cells than in the case of normal data programming, the channel portion is fixed to 0V while the source line is set to a positive voltage in the same manner as the normal data programming operation.
At the time of the above operation of programming data, in the select gate transistor provided on the source line side in the NAND cell connected to the “1” data writing bit line, a small amount of leakage current flows between the sources and drains in the state in which the sources and drains are set to the positive voltage and 0V, respectively while the control gate is set to 0V. Since the number of NAND cells in which the
Ho Hoai
Kabushiki Kaisha Toshiba
Le Thong
Pan Grace L.
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