Semiconductor memory device implemented with a test circuit

Details Semiconductor memory device implemented with a test circuit Semiconductor memory device implemented with a test circuit

2000-11-22

2003-03-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S201000, C365S226000, C365S225700

Reexamination Certificate

active

06529438

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in the Japanese Patent Application No. Hei 11-334971 filed in Nov. 25, 1999 and the Japanese Patent Application No. Hei 2000-287191 filed in Sep. 21, 2000 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a semiconductor memory device such as a static random access memory, and more particularly related to a semiconductor memory device implemented with a test circuit.
2. Prior Art
In the recent years, the increase in the storage capacity and the improvement of the power saving structure on the standby mode of semiconductor memory devices such as the static random access memory have been advanced. The occurrence frequency of defective bit locations tends to increase as the storage capacity increases so that, in the test process, defective memory cells are replaced by redundancy memory cells in accordance with the redundancy circuitry technique in order to recover the semiconductor memory device.
It is sometimes the case, however, that there is a memory call(s) through which a leakage current exceeding the allowable value is passed while the static random access memory including the defective memory cell normally operates without a problematic function. If there is such a memory cell, the consumption current in the standby mode is increased which decreases the device yield.
In accordance with the conventional semiconductor memory device as illustrated in
FIG. 1
, the location of a defective memory cell is detected as a path of a leakage current by a test circuit provided within the semiconductor memory device in order to cut off the leakage path via the defective memory by selectively melting and disconnecting a laser fuse through which the defective memory is connected to the power terminal so that the defective memory is replaced by a redundancy cells.
More specifically explaining, in the case of the semiconductor memory device as illustrated in
FIG. 1
, a “H” level operation mode switching signal S
6
is externally inputted to an external input circuit
92
through an external input terminal
91
. By this configuration, the output signal S
4
and the output signal S
5
of the external input circuit
92
become at the “L” level and at the “H” level respectively. An n-type transistor Q
2
receives at the gate thereof the output signal S
5
being pulled up to the “H” level and is then turned on, and therefore the output signal S
3
of a row address decoder
9
is transferred to one terminal of an NOR gate circuit
93
as the output signal S
2
.
By this configuration, the output signal S
3
of the row address decoder
96
is pulled up to the “H” level while, although not shown in the figure, the remaining output signals of the row address decoder
96
to the remaining lines (not shown in the figure) is pulled down to the “L” level. The output signal S
4
at the “L” level of the external input circuit
92
is input to the other input terminal of the NOR gate circuit
93
so that the output signal S
1
at the “H” level is input to the gate of the n-type transistor Q
1
, which is then turned off. By this configuration, the common electric power source line g
1
is separated from the electric power source, and therefore the memory cells M
11
to M
1
n are no longer supplied with electric energy while the remaining common electric power source lines (not shown in the figure) are maintained connected to the electric power source to supply the electric power to the remaining memory cells.
Furthermore, the output signal S
4
at the “L” level is input to the gate of the n-type transistor Q
5
while the output signal S
5
at the “H” level is input to the gate of the n-type transistor Q
4
and the gate of the p-type MOS transistor. As a result, the n-type transistor Q
5
and the p-type MOS transistor are turned off while the n-type transistor Q
4
is turned on so that the word line w
1
is grounded in order to be separated from the output signal S
3
of the row address decoder. By this configuration, no current is passed through the memory cells M
11
to M
1
m while the remaining memory cells are supplied with electric current.
It is determined, by selecting the respective lines in sequence and measuring the leakage current value for each selection in this manner, that a defective memory cell is included in the line being selected when the leakage current value is no lower than the allowable value. The defective line is then replaced with a redundancy line prepared in advance by melting the fuse F
1
connected to that line to disconnect the common electric power source line g
1
from the electric power source for cutting off the leakage current path.
The location of the memory cell as a leakage current path can be easily detected in this manner.
However, since recent semiconductor memory devices have been designed with large storage capacities, it is known that the memory cells of the memory cell arrays
50
are grouped into a plurality of blocks (l) to (n) in which the memory cells are arranged in matrices as illustrated in FIG.
2
.
A plurality of row address decoders
52
are located for each two cells while a row selection line
53
is extended from each row address decoder
52
. The row address decoder
52
serves to activate one of the row selection lines
53
as selected in accordance with the row addressing signal AIN which is input through an address decoder
60
. There are provided, at a plurality of ends of the blocks, block selection circuits
70
from which are extended block selection lines
55
, and word line selection circuits
56
receiving input signals from the row selection lines
53
and the block selection lines
55
.
Also, each pair of the memory cells
51
are located symmetrically in the vertical direction and commonly supplied with the electric power source through a common electric power source line VL which is located in parallel with the row selection line
53
.
In a normal operation mode, the memory cells
51
can be selected by selecting one of a plurality of the row selection lines
53
and one of a plurality of the block selection lines
55
in accordance with a desired address AIN and a desired address signal BIN in order to activate a desired one of the word lines
54
connected to the row selection line
53
and the block selection line
55
as selected. Data as selected can be read from the memory cells
51
by means of a read/write circuit
80
and output through an I/O terminal while desired data can be written to the memory cell
51
by means of a read/write circuit
80
through the I/O terminal.
When the semiconductor memory device is on the standby mode, all the word lines
54
are inactivated under the control of an internal circuit in response to an external signal as input.
Furthermore, in the case of recent semiconductor memory devices having been designed with large storage capacities, there are problems relating not only to the memory cell but also to the leakage current passing through a bit line, resulting in decrease of the device yield. Taking this point into consideration, when a defective function originating from a leakage current path through a bit line is recovered by the redundancy circuitry technique, the fuse elements as inserted to the electric power source connected to the bit line is disconnected by melting in order to replace the defective bit line by a redundancy cell as illustrated in
FIG. 3
showing an exemplary conventional semiconductor memory device of this kind.
The conventional semiconductor memory device as illustrated in
FIG. 3
is composed of a memory cell array consisting of a number of memory cells
100
arranged in the form of a matrix, control terminals (CE,WE,OE), internal circuits provided for the control terminals (a CE buffer, a WE buffer, an OE buffer), address terminals (an AINR terminal, an AINC terminal), internal circuit provided

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