Semiconductor memory device highly integrated in direction...

Details Semiconductor memory device highly integrated in direction... Semiconductor memory device highly integrated in direction...

2011-06-28

2011-06-28

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S230080

Reexamination Certificate

active

07969811

ABSTRACT:
First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets. Each of the first and third read bit lines is connected to a memory cell in one row in each of the sets, out of memory cells in a corresponding one of the columns. Each of the second and fourth read bit lines is connected to a memory cell in the other row in each of the sets, out of the memory cells in the corresponding one of the columns.

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Hiroki Noguchi et al., “A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing, ”IEEE Computer Society Annual Symposium on VLSI, 2007.

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