Semiconductor memory device having write recovery circuit struct

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365203, G11C 800

Patent

active

061282464

ABSTRACT:
A semiconductor memory device includes word lines, bit lines, and memory cells. Each of the memory cells is coupled to a corresponding one of the word lines and a corresponding one of the bit lines. The semiconductor memory device also includes a first node supplied with a first voltage level, a second node supplied with a second voltage level, a third node, and decoders. Each of the decoders is coupled among the second node, the third node, and a corresponding one of the word lines and also selectively couples either one of the second node and the third node to the corresponding word line in response to an address signal. The semiconductor memory device further includes a first voltage signal supply circuit, coupled to the first node and the third node, which couples the first node to the third node according to a control signal, and a second voltage signal supply circuit, coupled to the second node and the word lines, which couples the second node to the word lines according to the control signal.

REFERENCES:
patent: 5777935 (1998-07-01), Pantelakis et al.
patent: 5970018 (1999-10-01), Iwata et al.

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