Semiconductor memory device having write column select line...

Details Semiconductor memory device having write column select line... Semiconductor memory device having write column select line...

2002-08-16

2004-08-10

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Hardware for storage elements

Shields

C365S063000, C365S191000, C365S230060

Reexamination Certificate

active

06775170

ABSTRACT:

This application claims benefit and priority of Korean Patent Application No. 2002-2510, filed Jan. 16, 2002, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a write column select line or read column select line for shielding a signal line.
In a conventional semiconductor memory device, a signal line related to the operation of a semiconductor memory device, which is sensitive to the effect of the coupling capacitance of an adjacent signal line, is shielded with a power supply voltage line or ground voltage line for maintaining a stable voltage level and thus may provide for a stable signal property. A shielding line, such as the power supply voltage line or ground voltage line, may be arranged in a core region, which may include a memory cell array of the semiconductor memory device. Accordingly, a layout area of the semiconductor memory device might have to be increased in order to accommodate the shielding line.
In order to solve problems related to chip size and fast operating speeds, current mode signaling may be used instead of voltage mode signaling for conventional semiconductor memory devices, i.e., dynamic random access memory (DRAM). In the case of using current mode signaling, coupling of noise may occur due to a coupling capacitance between signal lines. That is, a signal of small voltage swings of, e.g., a several tens to several hundreds of millivolts (mV), may be affected by noise coupled thereto from an adjacent signal line. Such noise coupling may cause the memory device to malfunction.
FIGS. 1A and 1B
illustrate how a signal of one line may cause a malfunction on another adjacent line due to the coupling of noise from one line to the other. Referring to
FIGS. 1A and 1B
, a differential pair of signal lines D and /D may carry a differential signal of a small-swing of voltage difference &Dgr;V. The differential signal may be influenced by noise from an adjacent signal line NS. As a result, the signal of the differential pair D and /D may be corrupted to cause an invalid sensing operation marked by CASE
1
. One method of propagating a signal along a pair of differential signal lines D and /D may use current mode signaling. The voltage swing between the differential signal lines D and /D may be only several tens to several hundreds of millivolts (mV) and may be smaller than that of a CMOS voltage level.
FIGS. 2A and 2B
simplistically illustrate a conventional protective measure that may be used for preventing corruption of the signal of the signal line of FIG.
1
A. Referring to
FIGS. 2A and 2B
, to guard against invalid sensing of a signal of the pair of differential signal lines D and /D, the lines D and /D may be arranged to cross one another along their length. This arrangement may allow each of the differential signal lines D and /D to be equally affected by the coupling of noise from adjacent signal line NS. Ideally, the noise would be coupled equally to each of the lines of the differential pair to allow preservation of the differential signal. However, in this conventional arrangement, the effect of the coupling of the noise may be varied according to the relative position of each of the lines D and /D to the noise source. Thus, the conventional arrangement remains susceptible to noise of neighboring lines.
A RAS-to-CAS delay time (tRCD) and a RAS access time (tRAC) represent a couple of alternating current (AC) parameters of a semiconductor memory device. These parameters may reflect an operating speed of the semiconductor memory device and may be established within the core region of the semiconductor memory device. In order to permit improved speeds of operation of the semiconductor memory device, a column select circuit for controlling the input/output of data in the core region may be divided into separate portions operable under the control of a read column select line and write column select line. This method of controlling allows for more rapid transfer of data from within the core to a peripheral circuit when performing a read operation. Likewise, data of the peripheral circuit may also be more quickly transferred to the core region when performing a write operation. These features, thus, assist the speed of operation of the semiconductor memory device.
FIG. 3
is a block diagram illustrating a part of a conventional semiconductor memory device associated with controlling a column select circuit. In this conventional embodiment, the column select circuit is divided into separate portions operable under the control of a read column select line and a write column select line, respectively. The read column select line READ CSL, may be activated responsive to a read operation, while the write column select line WRITE CSL, may be activated responsive to a write operation. Each may be deactivated absent respective read or write operations of the read column select line READ CSL and the write column select line WRITE CSL. Each of the read column select line READ CSL and the write column select line WRITE CSL may be operable to preserve a constant voltage level (for example, of logic low or logic high).
Write column select circuits
32
and
34
may be operative to transfer data from data line pair D and /D, to a bit line pair BL and /BL in response to activation of a write column select signal W_CSL as propagated by the write column select line WRITE CSL. Once transferred to the bit line pair BL and /BL, the data may be stored in a core region
30
.
Read column select circuit
31
and
33
may transfer the data of core region
30
from bit line pair BL and /BL to data line pair D and /D in response to activation of a read column select signal R_CSL as propagated by the read column select line READ CSL.
FIG. 4A
illustrates layout of column select lines and a data line of the semiconductor memory device such as that of FIG.
3
.
FIG. 4B
is a timing diagram illustrating a potential invalid sensing operation of the data line pair of FIG.
4
A. In
FIG. 4B
, it is assumed that a first read column select line READ CSL
0
is activated after the activation of a second read column select line READ CSL
1
. Referring to
FIGS. 4A and 4B
, the signal of data line pair D and /D (to be sensed by a sensing operation during the activation of the first read column select line READ CSL
0
) may be corrupted as shown by the anomaly labeled CASE
3
in FIG.
4
B. The anomaly of CASE
3
may be caused by the coupling of noise, which may be associated with a signal transition of either the first read column select line READ CSL
0
or the second read column select line READ CSL
1
.
SUMMARY
In accordance with an exemplary embodiment of the present invention, a semiconductor memory device may comprise a write column select line or read column select line positioned for shielding a signal line related to operation of the semiconductor memory device.
According to one embodiment of the present invention, a semiconductor memory device comprises a signal line to propagate an operation signal associated with operation of the semiconductor memory device. A read column select line may propagate a read column select signal to control transfer of a data signal of a bit line to a data line. A write column select line may be operable to propagate a write column select signal to control transfer of a data signal of the data line to the bit line. One of the read column select line and the write column select line may be maintained at a predetermined logic level and may shield the signal line.
According a further embodiment of the present invention, the operation signal may comprise a data signal of a voltage smaller than a CMOS voltage level, and the deactivated column select signal may comprise a write column select signal.
According to another embodiment of the present invention, the logic level may comprise one of logic low level or logic high level.
According to another embodiment of the present invention, a semicond

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