Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2002-08-19
2004-01-06
Le, Thong Quoc (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230030, C365S189040
Reexamination Certificate
active
06674685
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and, particularly to a semiconductor memory device allowing a data signal to be rewritten thereinto.
2. Description of the Background Art
FIG. 10
is a circuit block diagram showing a principal portion of a conventional dynamic random access memory (hereinafter DRAM). Referring to
FIG. 10
, the DRAM includes a plurality of memory cells MC arranged in rows and columns, a word line WL provided correspondingly to each row, a pair of bit lines BL and /BL provided correspondingly to each column, and a pair of write data lines WDL and /WDL. The DRAM further includes a write column select gate
50
, a sense amplifier
55
and an equalizer
60
that are provided correspondingly to each column.
Write column select gate
50
includes N-channel MOS transistors
51
-
54
. N-channel MOS transistors
51
and
52
are connected in series between bit line BL and write data line WDL, and N-channel MOS transistors
53
and
54
are connected in series between bit line /BL and write data line /WDL. N-channel MOS transistors
51
and
53
have respective gates connected to a write column select line WCSL and N-channel MOS transistors
52
and
54
have respective gates receiving signal WDE. Signal WDE is set to L level (logical low level) for write masking and set to H level (logical high level) in normal operation. When signal WDE has H level and write column select line WCSL designated according to column address signal CA is set to H level which is the selection level, N-channel MOS transistors
51
-
54
of the corresponding column are turned on to couple paired bit lines BL and /BL and paired write data lines WDL and /WDL.
Sense amplifier
55
includes N-channel MOS transistors
56
and
57
and P-channel MOS transistors
58
and
59
. N-channel MOS transistors
56
and
57
are connected respectively between bit lines BL and /BL and a node N
51
, and have respective gates connected respectively to bit lines /BL and BL. P-channel MOS transistors
58
and
59
are connected respectively between bit lines BL and/BL and a node N
52
, and have respective gates connected respectively to bit lines /BL and BL. Nodes N
51
and N
52
receive sense amplifier activation signals SNL and SPL respectively. In a standby state, sense amplifier activation signals SNL and SPL are each set to potential VCC/2, i.e., a half of a power supply potential VCC. In an active state, sense amplifier activation signals SNL and SPL are set respectively to L and H levels. Sense amplifier activation signals SNL and SPL are set to L and H levels respectively to activate sense amplifier
55
which in turn amplifies a minute or considerably small potential difference between corresponding paired bit lines BL and /BL up to power supply potential VCC.
Equalizer
60
is activated when bit line equalize signal BLEQ is set to the activation level, L level, and accordingly precharges corresponding paired bit lines BL and /BL to bit line precharge potential VBL (=VCC/2).
FIG. 11
is a timing chart illustrating a write operation of the DRAM shown in FIG.
10
. In a standby state, word line WL is set to the non-selection level, L level, to inactivate memory cell MC. Write column select line WCSL is also set to the non-selection level, L level, to make write column select gate
50
nonconductive. Equalizer
60
is activated to precharge paired bit lines BL and /BL to precharge potential VCC/2. Sense amplifier activation signals SPL and SNL are set to the immediate level VCC/2 to inactivate sense amplifier
55
. Here, signal WDE is set to H level.
First, active command ACT and row address signal RA are provided, equalizer
60
is inactivated, and word line WL of a row according to row address signal RA is raised to the selection level, H level. Word line WL is thus set to H level to activate each memory cell MC corresponding to that word line WL. Then, a minute potential difference of a polarity according to data stored in memory cell MC is generated between paired bit lines BL and /BL. Then, sense amplifier activation signals SPL and SNL are set to H and L levels respectively to activate sense amplifier
55
. Accordingly, the potential difference between paired bit lines BL and /BL is amplified to power supply potential VCC.
Second, write command WRT and column address signal CA are provided. Write column select line WCSL of a column according to column address signal CA is raised to the selection level, H level, to make write column select gate
50
of that column conductive. Accordingly, paired bit lines BL and /BL of that column and paired write data lines WDL and /WDL are coupled. In advance, write data lines WDL and /WDL are set respectively at L and H levels for example according to a write data signal. Then, the levels of respective bit lines BL and /BL of the selected column are converted to the levels of respective write data lines WDL and /WDL. The levels of bit lines BL and /BL of any non-selected column are maintained. After a predetermined time has passed, write column select line WCSL is lowered to the non-selection level, L level.
Third, precharge command PRE is provided. Word line WL is lowered to the non-selection level, L level, to inactivate memory cell MC. Sense amplifier activation signals SPL and SNL are set to the intermediate level, VCC/2, to inactivate sense amplifier
55
. Equalizer
60
is activated and paired bit lines BL and /BL are set to bit line precharge potential VBL. In this way, the data signal is written.
FIG. 12
is a circuit block diagram showing a principal portion of another conventional DRAM. Referring to
FIG. 12
, this DRAM differs from the DRAM in
FIG. 10
in that the former includes a write column select gate
61
instead of write column select gate
50
. Write column select gate
61
includes N-channel MOS transistors
62
-
65
. N-channel MOS transistors
62
and
63
are connected in series between bit line BL and a line of a ground potential GND. N-channel MOS transistors
64
and
65
are connected in series between bit line /BL and the line of ground potential GND. N-channel MOS transistors
62
and
64
have respective gates both connected to write column select line WCSL, and N-channel MOS transistors
63
and
65
have respective gates connected respectively to write data lines /WDL and WDL.
When write column select line WCSL is raised to the selection level, H level, N-channel MOS transistors
62
and
64
are turned on. When write data lines WDL and /WDL have H and L levels respectively, N-channel MOS transistor
65
is turned on while N-channel MOS transistor
63
is turned off. Then, bit line /BL is lowered to L level, and sense amplifier
55
raises bit line BL to H level. When write data lines WDL and /WDL have L and H levels respectively, N-channel MOS transistor
63
is turned on while N-channel MOS transistor
65
is turned off. Then, bit line BL is lowered to L level and sense amplifier
55
raises bit line /BL to H level. Except for the above-described details, the DRAM shown in
FIG. 12
has the same structure and operation as those of the DRAM shown in FIG.
10
and description thereof is not repeated here.
High-speed writing into conventional DRAMs is possible in a page mode, in which column selection is performed multiple times successively for one activated memory-cell row, since it is merely necessary that write command WRT is input multiple times after active command ACT is applied once. However, in a random access mode in which row address signal RA and column address signal CA are changed each time write operation is carried out, the three steps shown in
FIG. 11
are required for each write operation, which makes it difficult to speed up the write operation.
Specifically, random access of at least 50 MHz is possible to a static random access memory (hereinafter SRAM) while random access of as low as approximately 22 MHz is merely possible to a DRAM. This results in an obstacle for the DRAM to achieve functions of the SRAM implemented in a s
Le Thong Quoc
McDermott & Will & Emery
Renesas Technology Corp.
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