Semiconductor memory device having write column select gate

Details Semiconductor memory device having write column select gate Semiconductor memory device having write column select gate

2002-06-11

2003-11-04

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S189050

Reexamination Certificate

active

06643214

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device capable of rewriting a data signal.
2. Description of the Background Art
FIG. 14
is a circuit block diagram which shows the main parts of a conventional dynamic random access memory (referred to as “DRAM” hereinafter). In
FIG. 14
, this DRAM includes a plurality of memory MC which are arranged in rows and columns, word lines WL which are provided to correspond to the rows, respectively, bit line pairs BL and /BL which are provided to correspond to the columns, respectively, a write data line pair WDL and /WDL. This DRAM also includes write column select lines WCSL, write column select gates
50
, sense amplifiers
55
and equalizers
56
.
Each write column select gate
50
includes N-channel MOS transistors
51
to
54
. N-channel MOS transistors
51
and
52
are connected in series between bit line BL and write data line WDL and N-channel MOS transistors
53
and
54
are connected in series between bit line /BL and write data line /WDL. The gates of N-channel MOS transistors
51
and
53
are both connected to write column select line WCSL and those of N-channel MOS transistors
52
and
54
both receive a write driver enable signal WDE. Signal WDE is set at “L” level during write masking and set at “H” level during an ordinary operation. If write column select line WCSL in the column according to a column address signal CA is set at a selected level of “H” level while signal WDE is set at “H” level, N-channel MOS transistors
51
to
54
in the column become conductive and bit line pair BL and /BL is connected to write data line pair WDL and /WDL.
Each sense amplifier
55
is activated when sense amplifier activation signals SNL and SPL are set at “L” level and “H” level, respectively and amplifies a micro-potential difference which is generated between corresponding bit lines BL and /BL, to a power supply voltage VCC. Each equalizer
56
is activated when a bit line equalization signal EQ is set at active level of “L” level and precharges corresponding bit lines BL and /BL with a bit line precharge potential VBL (=VCC/2).
Next, the write operation of this DRAM will be described. In a standby state, each word line WL is set at an unselected level of “L” level, each memory cell MC is inactivated, each write column select line WCSL is set at unselected level of “L” level and each write column select gate
50
is set nonconductive. In addition, each equalizer
56
is activated, each bit line pair BL and /BL is precharged with bit line precharge potential VCC/2, sense amplifier activation signals SPL and SNL are set at intermediate level of VCC/2 and each sense amplifier
55
is inactivated. Further, signal WDE is set at “H” level.
First, equalizer
56
is inactivated and word line WL in a row according to a row address signal RA is raised to selected level of “H” level. When the level of word line WL is raised to selected level of “H” level, each memory cell MC corresponding to word line WL is activated and a micropotential difference with a polarity according to the stored data of memory cell MC is generated between bit line pair BL and /BL. Then, sense amplifier activation signals SPL and SNL are set at “H” level and “L” level, respectively, thereby activating sense amplifier
55
and amplifying the potential difference between bit line pair BL and /BL to power supply voltage VCC.
Next, the level of write column select line WCSL in a column according to a column address signal CA is raised to selected level of “H” level, thereby making write column select gate
50
in the column conductive and coupling bit line pair BL and /BL to write data line pair WDL and /WDL in the column. Write data lines WDL and /WDL are set at, for example, “L” level and “H” level in accordance with a write data signal, respectively. Therefore, the levels of bit lines BL and /BL in the selected column are rewritten to those of write data lines WDL and /WDL, respectively. The levels of bit lines BL and /BL in unselected columns are kept as they are. Write column select line WCSL is let fall to unselected level of “L” level after the passage of predetermined time.
Next, word line WL is let fall to unselected level of “L” level, memory cell MC is inactivated, sense amplifier activation signals SPL and SNL are made intermediate level VCC/2, sense amplifier
55
is inactivated, equalizer
56
is activated, and bit line pair BL and /BL is set to have bit line precharge potential VBL. In this way, a data signal is written.
Further,
FIG. 15
is a circuit block diagram which shows the main parts of another conventional DRAM. Referring to
FIG. 15
, this DRAM differs from DRAM shown in
FIG. 14
in that write column select gate
50
is replaced by a write column select gate
61
. Write column select gate
61
includes N-channel MOS transistors
62
to
65
. N-channel MOS transistors
62
and
63
are connected in series between bit line BL and the line of a ground potential GND, and N-channel MOS transistors
64
and
65
are connected in series between bit line /BL and the line of ground potential GND. The gates of N-channel MOS transistors
62
and
64
are both connected to write column select line WCSL and the gates of N-channel MOS transistors
63
and
65
are connected to write data lines /WDL and WDL, respectively.
When the level of write column select line WCSL is raised to selected level of “H” level, N-channel MOS transistors
62
and
64
become conductive. If write data lines WDL and /WDL are at “H” level and “L” level, respectively, then N-channel MOS transistor
65
becomes conductive, N-channel MOS transistor
63
becomes nonconductive, the level of bit line /BL is let fall to “L” level and the level of bit line BL is raised to “H” level by sense amplifier
55
. If write data lines WDL and /WDL are at “L” level and “H” level, respectively, then N-channel MOS transistor
63
becomes conductive, N-channel MOS transistor
65
becomes nonconductive, the level of bit line BL is let fall to “L” level and the level of bit line /BL is raised to “H” level by sense amplifier
55
. Since the other configurations and operations of DRAM shown in
FIG. 15
are the same as those of DRAM shown in
FIG. 9
, they will not be repeatedly described herein.
Conventional DRAMs have, however, the following disadvantages. In case of DRAM shown in
FIG. 14
, it is necessary to extend a wiring for write driver enable signal WDE to each write column select gate
50
. However, it is difficult to secure a region to provide the wiring for signal WDE in a memory mat in which word lines WL, bit line pairs BL, /BL, write data line pair WDL, /WDL, a read data line pair (not shown), write column select lines WCSL, the line of power supply potential VCC, the line of ground potential GND and the like are complicatedly arranged.
Furthermore, the gates of many N-channel MOS transistors
53
and
54
are connected to respective signal WDE wirings and the load capacitance of each signal WDE wiring increases. As a result, it is necessary to provide a repeater on each signal WDE wiring to change the level of signal WDE at high rate, to hierarchize the signal WDE wiring to reduce consumption current and to secure a region for arranging the repeater and a circuit for changing over hierarchies in the memory mat. The memory mat is thereby disadvantageously divided by such a region and a layout area is disadvantageously made larger.
Moreover, in case of DRAM shown in
FIG. 15
, the gates of many N-channel MOS transistors
63
and
65
are connected to write data lines WDL and /WDL, respectively, and the load capacitances of write data lines WDL and /WDL increase. Due to this, it is necessary to interpose repeaters on write data lines WDL and /WDL, respectively to change the levels of write data lines WDL and /WDL at high rate, and to secure a region for arranging the repeaters and a circuit for changing hierarchies in the memory mat. The memory mat is thereby disadv

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