Semiconductor memory device having wordline enable signal...

Details Semiconductor memory device having wordline enable signal... Semiconductor memory device having wordline enable signal...

2007-09-25

2007-09-25

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000

Reexamination Certificate

active

11330819

ABSTRACT:
Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline enable driver is arranged in a row decoder region outside a memory array region, and the wordline enable signal lines are formed of an uppermost metal layer among three metal layers constituting the semiconductor memory device. Each of the wordline enable signal lines is connected to a sub-wordline driver, rather than to a pair of sub-wordline drivers. In other words, the wordline enable signal lines vertically and horizontally extend forming an inverse L shape.

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English language abstract of Korean Publication No. 2000-0045415.
English language abstract of Japanese Publication No. 06-195964.
English language abstract of Japanese Publication No. 09-045077.

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