Semiconductor memory device having word lines driven by row...

Details Semiconductor memory device having word lines driven by row... Semiconductor memory device having word lines driven by row...

2000-03-17

2001-08-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S051000, C365S063000

Reexamination Certificate

active

06282147

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device including a plurality of memory banks (i.e., storage units which are individually controlled), in particular, one having a plurality of memory blocks each of which includes a plurality of memory banks.
This application is based on Patent Application No. Hei 11-94203 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
FIG. 12
shows the general structure of a conventional semiconductor memory device. In the following explanations, it is assumed for convenience that the semiconductor memory device is a DRAM (dynamic random access memory) having a storage capacity of 256 Mbit. This semiconductor memory device consists of 32 banks indicated by reference numerals Ba
0
to Ba
31
in FIG.
12
. That is, in comparison with the SDRAM (synchronous DRAM) which generally consists of 4 banks or the like, the memory device shown in
FIG. 12
includes a larger number of banks. The reason for dividing the whole memory area into a plurality of banks follows: In the DRAM or the like, the operation of storing or deleting data in or from the internal memory cells is performed using the charge or discharge process; thus, the operation speed in the semiconductor memory device cannot be as high as the transfer speed of the bus connected to the memory device. Therefore, the memory cell array in the semiconductor memory device is divided into a plurality of banks so as to perform a parallel process, thereby virtually performing a high-speed operation having a speed as high as the bus operation.
Each bank can be regarded as a logically independent memory, and as explained above, while the banks are activated in turn, serial data input/output operation is performed with respect to each target cell, thereby realizing a high-speed general operation. As with general DRAMs, the semiconductor memory device shown in
FIG. 12
has a two-dimensional memory cell arrangement. In order to designate one of the memory cell arrays, the address signal supplied to the semiconductor memory device includes a bank address for designating a bank, a row address for designating a row in the X direction, and a column address for designating a column in the Y direction. The upper portion of the address signal is assigned to the bank address. The target memory cell is accessed by designating the target bank using the bank address, and then designating the memory cell using the row and column addresses.
More specifically, the semiconductor memory device shown in
FIG. 12
has 4 blocks, each consisting of 32 banks. For example, the areas indicated by reference numerals
1
-
1
and
1
-
2
form a single block. In area
1
-
1
or
1
-
2
, 32 Mbit (256 Mbit/8) memory cells are integrated, and each area is called a “memory cell array block” in the following explanations. Memory cell array blocks
1
-
1
and
1
-
2
,
1
-
3
and
1
-
4
,
1
-
5
and
1
-
6
, and
1
-
7
and
1
-
8
respectively form pairs, and 32 banks Ba
0
to Ba
31
are assigned to each pair.
Each memory cell array block has a “×4 bit” structure. When a specific address is designated or read out, 32 bit data is output from 32 I/O lines. In
FIG. 12
, each arrow indicates “4 I/O”, and eight “4 I/O” (i.e., 4 I/O×8) arrows output from each memory cell array block indicates the above operation. Accordingly, if data is read out from a bank of the memory cell array blocks
1
-
1
and
1
-
2
, a 32 bit data is output in total. The 32 bit data is then parallel-serial converted. The data from the memory cell array blocks
1
-
1
and
1
-
2
is combined with a 32 bit data from the memory cell array blocks
1
-
5
and
1
-
6
, so that a 8 DQ×8 cycle data is output via circuit block
6
(explained later) to the outside of the device. A similar operation is performed in the memory cell array blocks
1
-
3
and
1
-
4
and the memory cell array blocks
1
-
7
and
1
-
8
.
Circuit blocks
2
-
1
to
2
-
4
are provided between the two memory cell array blocks of each of 4 pairs. Each circuit block comprises a data amplifier (see “DA” in
FIG. 12
) for amplifying data read out from the memory cell array via a sense amplifier (not shown) and the like, a write amplifier (see “WA” in
FIG. 12
) used when data is written in the memory cell array, a column decoder for decoding the column address of the relevant memory cell array block, and so on.
Reference numerals
3
-
1
to
3
-
8
indicate row decoders (see “Row Dec.” in
FIG. 12
) for decoding the row address in the address signal and outputting a decoded signal obtained by the decoding operation. These row decoders
3
-
1
to
3
-
8
correspond to each memory cell array block.
The circuit blocks
4
-
1
and
4
-
2
are arranged in the upper and lower sides of circuit blocks
5
to
7
(explained later). Each of the circuit blocks
4
-
1
and
4
-
2
comprises row pre-decoding circuit (see “Row pre dec.” in
FIG. 12
) for pre-decoding the row address before the decoding operation of the row decoder, and a redundancy circuit (see “Row red.” in
FIG. 12
) for performing a redundancy process for recovering a disordered memory cell array in the row direction.
The circuit block
5
comprises a booster circuit (see “Vboot” in
FIG. 12
) generally used when the word line is activated, a fuse (see “Fuse” in
FIG. 12
) used for the redundancy process, a reference potential generating circuit (see “Vref” in
FIG. 12
) for generating a reference potential used for reducing the internal voltage, and so on.
The circuit block
6
comprises an input/output interface circuit (see “I/F” in FIG.
12
), a circuit for adjusting the skew of the clock used in the semiconductor memory device (see “DLL (delayed lock loop)” in FIG.
12
), a known input/output pad (see “Bonding Pad” in FIG.
12
), and so on.
The circuit block
7
comprises the above “Vboot”, “Fuse”, and a circuit for generating a substrate potential (see “BBG (back bias generator)” in FIG.
12
), and so on.
FIG. 13
is an enlarged view showing the circuit related to memory cell array block
1
-
1
. In a general SDRAM or the like, the row decoder, column decoder, sense amplifier, and the like are separately provided for each bank. In contrast, in the semiconductor memory device as shown in
FIGS. 12 and 13
, a row decoder is provided for 16 banks (i.e., Ba
0
to Ba
15
, or Ba
16
to Ba
31
). Additionally, as shown in
FIG. 13
, sense amplifier area
10
is provided between the banks. In the area
10
, a sense amplifier (may be abbreviated as “S/A”, hereinbelow) for reading out data from the memory cell array, and the like are provided.
A bank selecting logic circuit (not shown) is provided close to the row decoder
11
. The column bank selecting signals CBS
0
to CBS
15
generated by the bank selecting logic circuit are respectively supplied to the banks Bank
0
to Bank
15
, and each bank selecting signal can be independently made effective, thereby activating the corresponding bank. The bank selecting logic circuit is provided in the circuit blocks
4
-
1
and
4
-
2
shown in FIG.
12
. When the bank Bank
1
is being activated, the bank selecting operation using the bank selecting signals CBS
1
is performed in the sense amplifier areas adjacent to Bank
1
. These column bank selecting signals CBS
0
to CBS
15
can be obtained by decoding the bank address included in the above-explained address signal. As later explained, each column bank selecting signal uses two signal lines (inverted
on-inverted); however, a single signal line is described in
FIG. 13
for convenience.
The row decoder
11
decodes the row address included in the address signal, thereby selecting one of the word lines WL indicated by broken lines in FIG.
13
. The column decoder
12
decodes all bits (7 bits in the later-explained embodiment of the present invention) of the column address included in the address signal, thereby selecting one of column selecting signals YSW (indicated by thick lines in
FIG. 13
) by using a column s

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