Semiconductor memory device having wiring with lead portions...

Details Semiconductor memory device having wiring with lead portions... Semiconductor memory device having wiring with lead portions...

2011-04-19

2011-04-19

Phung, Anh (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S773000, C257S784000, C257SE23010, C257SE23141

Reexamination Certificate

active

07928580

ABSTRACT:
A semiconductor memory device includes a first wiring region and a second wiring region located adjacent to the first wiring region. First lines located in the first wiring region include a first portion, a first lead portion and first inclined portion. Second lines located in the second wiring region include a second portion, a second lead portion and a second inclined portion. The first and second portions are located in parallel with a same pitch, the first and second lead portions are located with a pitch which is larger than the pitch of the first and second portions, the first and second inclined portions extend the same direction at a predetermined angle.

REFERENCES:
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 2006/0038292 (2006-02-01), Minami et al.
patent: 2000-22895 (2000-01-01), None
patent: 2000-76880 (2000-03-01), None
patent: 2006-60133 (2006-03-01), None
U.S. Appl. No. 11/842,615, filed Aug. 21, 2007, Futatsuyama.

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