Semiconductor memory device having variable precharging period

Details Semiconductor memory device having variable precharging period Semiconductor memory device having variable precharging period

1994-02-02

1995-01-03

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

365203, G11C 800

Patent

active

053792653

ABSTRACT:
A selected static type random access memory cell changes associated bit lines between a positive high voltage level and a ground voltage level in a write-in sequence and between the positive high voltage level and a middle voltage level in a read-out sequence, and a timing controller monitors the bit lines for producing an enable signal supplied to a word line driving unit and for canceling a precharge controlling signal supplied to a pull-up/balancing unit upon arrival of either bit line at the middle voltage level, thereby preventing the static type random access memory cell from connection with the associated bit lines with a large potential difference.

REFERENCES:
patent: 4712197 (1987-12-01), Sood
patent: 4872143 (1989-10-01), Sumi

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