Semiconductor memory device having trench and stacked polysilico

Details Semiconductor memory device having trench and stacked polysilico Semiconductor memory device having trench and stacked polysilico

1987-12-08

1990-01-23

Clawson, Jr., Joseph E.

357 55, 357 41, H01L 2978, H01L 2906, H01L 2702

Patent

active

048961973

ABSTRACT:
A first impurity region is formed on the inner surface of a trench formed on the major surface of a semiconductor substrate. The trench is filled with a vertical portion of a first electric conductor having a reversed L-shaped cross section through an insulating film. A first transistor having a first impurity region serving as a source/drain region is formed on the semiconductor substrate. A second impurity region serving as a source/drain region of a second transistor is formed on the major surface of the semiconductor substrate and spaced from the trench. A second electric conductor having a reversed L-shaped cross section for connecting the vertical portion to the second impurity region is formed, and a horizontal portion of the second electric conductor is formed to be stacked on a horizontal portion of the first electric conductor with an insulating film formed therebetween.

REFERENCES:
patent: 4419743 (1983-12-01), Taguchi et al.
patent: 4460911 (1984-07-01), Salters
patent: 4716548 (1987-12-01), Mochizuki
IEDM 84: "Trench Capacitor Leakage in MBIT DRAMS", by M. Elahy et al., 9.6 1984, pp. 248-251.

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