Semiconductor memory device having test mode

Details Semiconductor memory device having test mode Semiconductor memory device having test mode

1993-04-16

1994-12-06

Fears, Terrell W.

Static information storage and retrieval

Addressing

365201, 36518901, G11C 1300

Patent

active

053717104

ABSTRACT:
A memory cell array, which is one of a plurality of divisional memory cell arrays, is selected by an address signal. One of the word lines incorporated in the memory cell array is selected by a row decoder. An OR circuit is supplied with a control signal for setting a burn-in test mode, and with the address signal for selecting the memory cell array. In the burn-in test mode, since the level of the control signal becomes high, the output level of the OR circuit becomes high irrespective of the address signal. Thus, the overall memory cell arrays are simultaneously selected, and hence more word lines than those accessed in a normal operation mode are simultaneously accessed.

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