Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-01-29
1998-11-24
Nelms, David C.
Static information storage and retrieval
Addressing
Sync/clocking
36515901, G11C 800
Patent
active
058417303
ABSTRACT:
A semiconductor memory device capable of shortening data reading time in a first read cycle after the mode has been changed from a write mode to a read mode while maintaining high-speed cycle time when data is written despite simple structure, the semiconductor memory device having a memory cell array having a plurality of dynamic memory cells, to which data can be written, data line pairs to which data read from the memory cells and data which must be written on the memory cells are transferred, a write driver for driving the data line pairs in accordance with write data supplied from outside when data is written to the memory cells and an equalizing circuit for setting the data line pairs to an intermediate potential whenever the data line pairs are operated by the write driver.
REFERENCES:
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5539693 (1996-07-01), Koshikawa et al.
patent: 5566108 (1996-10-01), Kitamura
patent: 5581512 (1996-12-01), Kitamura
patent: 5592434 (1997-01-01), Iwamoto et al.
Kai Yasuyuki
Nagaba Katsushi
Ohshima Shigeo
Ho Hoai V.
Kabushiki Kaisha Toshiba
Nelms David C.
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