Semiconductor memory device having sub-word line driving circuit

Details Semiconductor memory device having sub-word line driving circuit Semiconductor memory device having sub-word line driving circuit

1999-03-29

2000-05-30

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 51, 365 63, 36523003, G11C 800

Patent

active

060698381

ABSTRACT:
A semiconductor memory device having a sub-word line driving circuit overcoming disadvantages of a conventional semiconductor memory device having a sub-word line driving circuit in that it requires additional NMOS transistors with their gates applied with a predecoding signal in order to connect all sub-word lines to the ground which may be floated during the operation of the sub-word line driving circuit, and thus a layout of the device is complicated and a size of the memory chip is increased, can simplify the device layout and reduce the memory chip size by using the NMOS transistor connecting the adjacent sub-word lines which are applied with an identical predecoding signal but receive different inverted global word line enable signals.

REFERENCES:
patent: 5781498 (1998-07-01), Suh
patent: 5835439 (1998-11-01), Suh
patent: 5943289 (1999-08-01), Ahn et al.
patent: 5966341 (1999-10-01), Takahashi et al.
patent: 5970003 (1999-10-01), Miyatake et al.

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