Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Patent
1991-02-26
1994-03-29
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
365149, 257296, 257304, 257311, G11C 1124
Patent
active
052987752
ABSTRACT:
A DRAM comprising word lines parallel to an X-axis and bit lines parallel to a Y-axis wherein the memory cell consists of a transistor and a stacked-type charge-storage capacitor is disclosed. The storage node electrode of the stacked-type charge-storage capacitor is formed to project on the surface of the silicon substrate a rectangle of which the major sides are oblique to the X-axis and Y-axis or a pattern consisting of at least two different rectangles. Thereby the perimeter of the storage node electrode becomes more than that in the prior art. This enables the realization of charge-storage capacitors having larger capacitance value than in a conventional DRAM under the same manufacturing conditions. This effect is marked under the conditions where the film thickness of the storage node electrode is more than 1/2 of the minimum feature size, and the distance between two adjacent storage node electrodes is equal to the minimum feature size.
REFERENCES:
patent: 4651183 (1987-03-01), Lange et al.
patent: 5012309 (1991-04-01), Nakayama
Mintel William
NEC Corporation
Potter Roy
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