Semiconductor memory device having stacked gate including...

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185210, C365S185230

Reexamination Certificate

active

07929344

ABSTRACT:
A semiconductor memory device includes a memory cell, a bit line, a source line, a detection circuit, and a sense amplifier. The memory cell holds or more levels of data. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The detection circuit detects a current flowing through the source line during a read operation and a verify operation on the data. The sense amplifier reads the data by sensing a current flowing through the bit line during the read operation and the verify operation. Whether or not the sense amplifier reads the same data plural times is determined according to a current amount detected by the detection circuit.

REFERENCES:
patent: 7443757 (2008-10-01), Cernea et al.
patent: 2002/0139999 (2002-10-01), Hirano
patent: 2004/0057318 (2004-03-01), Cernea et al.
patent: 2007/0014152 (2007-01-01), Shibata et al.
patent: 2008/0094903 (2008-04-01), Maejima et al.
patent: 2009/0161433 (2009-06-01), Lee et al.
patent: 2006-500727 (2006-01-01), None
patent: 2006-79803 (2006-03-01), None
patent: 2009-163793 (2009-07-01), None
patent: WO 2006/107706 (2006-10-01), None

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