Semiconductor memory device having split operation and capable o

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36523001, 36523003, 36523008, G11C 700, G11C 1140

Patent

active

052375366

ABSTRACT:
In a semiconductor memory device comprising a plurality of groups of memory cell blocks, a plurality of groups of predecoder input signal lines respectively connected to predecoders in the memory cell block groups, and a predecoder input signal generator. The predecoder input signal generator sets the predecoder input signal lines of the selected group to either the high level or the low level in accordance with the external address information. A clamping circuit is provided to clamp substantially half the predecoder input signal lines of the unselected group to the high level, and the remaining half to the low level. Because one half of the predecoder input signal lines of the unselected group is clamped to the high level and the remaining half of the unselected group is clamped to the low level, their line loads serve as decoupling capacitors both at the charging and discharging of the predecoder input signal lines of the selected group, so that the power supply noise is reduced in both occasions.

REFERENCES:
patent: 4542486 (1985-09-01), Anami
patent: 4636982 (1987-01-01), Takemae et al.
patent: 4768166 (1988-08-01), Anami

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