Semiconductor memory device having serial addressing and operati

Details Semiconductor memory device having serial addressing and operati Semiconductor memory device having serial addressing and operati

1989-01-12

1990-11-06

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sequential

36518912, G11C 800

Patent

active

049691260

ABSTRACT:
An IC card comprises an integrated circuit having a memory circuit and a shift register formed thereon in a package. The memory circuit is selectively disabled by an external signal. The memory circuit comprises a plurality of data terminals for inputting and outputting data, one of which connected to a serial input terminal of the shift register. Address information is serially applied bit by bit from outside to the data terminal when the memory circuit is in the disabled state. The address information is converted into parallel address signals by the shift register to be applied to the address terminals of the memory circuit, so that the number of the external terminals can be reduced. A binary digit string in accordance with an exhaustive random sequence is used as the address information applied in series, thereby increasing the speed of the data transfer.

REFERENCES:
S. Funatsu et al., "Designing Digital Circuits with Easily Testable Consideration", 1978 Semiconductor Test Conference, Digest of Papers, pp. 89-102.
G. Hoffman de Visme, "Binary Sequences", 1971.

Affiliated with

Also associated with

Rating

Semiconductor memory device having serial addressing and operati does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having serial addressing and operati, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having serial addressing and operati will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1311343